NVIDIA Jetson TX2 NX DG-10141-001_v1.1 | 66
Chapter 12. PADS
Jetson TX2 NX signals that come from Tegra X2 may glitch when the associated power rail is
enabled. This may affect pins that are used as GPIO outputs. Designers should take this into
account. GPIO outputs that must maintain a low state even while the power rail is being
ramped up may require special handling.
12.1 Internal Pull-ups for Dual-Voltage
Block Pins Powered at 1.8V
Several of the MPIO pads are on blocks designed to be powered at either 1.8V or 3.3V. These
blocks are powered at 1.8V on Jetson TX2 NX, and the internal pull-up at initial Power-ON is
not effective. The signal may only be pulled up a fraction of the 1.8V rail. Once the system
boots, software can configure the pins for 1.8V operation and the internal pull-ups will work
correctly. If these signals need the pull-ups during Power-ON, external pull-up resistors
should be added. The following list is the affected pins list. These are the Jetson TX2 NX pins
on the dual-voltage blocks powered at 1.8V with Power-ON reset default of Internal pull-up
enabled.
SDMMC_DAT0
SDMMC_DAT1
SDMMC_DAT2
SDMMC_DAT3
SDMMC_CMD
12.2 Schmitt Trigger Usage
The MPIO pins have an option to enable or disable Schmitt-trigger mode on a per-pin basis.
This mode is recommended for pins used for edge-sensitive functions such as input clocks, or
other functions where each edge detected will affect the operation of a device. Schmitt-trigger
mode provides better noise immunity and can help avoid extra edges from being “seen” by the
Tegra X2 inputs. Input clocks include the I2S and SPI clocks (I2Sx_SCLK and SPIx_SCK) when
Tegra X2 is in slave mode. The FAN_TACH pin [GPIO8] is another input that could be affected
by noise on the signal edges. The SDMMC_CLK pin, while used to output the clock, also
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