82
Parameters Address (command): Specify the address from which to start searching for the
timer/counter instruction in four digits of BCD.
Timer/Counter instruction (command): Specify in four letters the instruction
used to create the timer/counter (see below).
Timer/Counter number (command): Specify the timer/counter number used
to define the timer/counter.
Timer/Counter instruction
Instruction Timer/Counter
OP1 OP2 OP3 OP4
number
T M H W HIGH-SPEED TIMER
WAIT (TMHW<015>)
000 to 0511
(CVM1-CPU01-EV2
T I M W TIMER WAIT
(TIMW<013>)
and CV500)
0000 to 1023 (other
C N T W COUNTER WAIT
(CNTW<014>)
CPUs)
T I M H HIGH-SPEED TIMER
(TIMH(015))
T T I M ACCUMULATIVE
TIMER (TTIM(120))
C N T R REVERSIBLE
COUNTER (CNTR(012))
T I M space TIMER (TIM)
C N T space COUNTER (CNT)
Note A total of four letters are required to specify the instruction. Be sure to include a
space where necessary.
Operand (response): Specifies whether a constant or word was used to define
the timer/counter and, if a word was used, specifies the data area of the word
(see below).
SV or address (response): The SV of the specified instruction in BCD or the
address of the word used for the SV.
Operand
Constant/Area SV
OP1 OP2 OP3 OP4
(see notes)
C O N space Constant 0000 to 9999
C I O space CIO Area 0000 to 2555
G R space space CPU Bus Link Area 0000 to 0255
A R space space Auxiliary Area 0000 to 0511
T I M space Timer Area
0000 to 0511 or
C N T space Counter Area
0000 to 1023
D M space space DM Area
00000 to 08191 or
D M
*
space Indirect DM address
00000 to 09999
E M space space EM Area
00000 to 09999
E M
*
space Indirect EM address
D R space space Data Register 0000 to 0002
I R space space Index Register 0000 to 0002
, I R space Indirect index
register address
0000 to 0002 (offsets and
other details cannot be
read)
Note 1. A total of four letters are required to specify the operand. Be sure to include
spaces where necessary.
2. Word address ranges depend on the CPU being used. Refer to the CV-se-
ries Operation Manual: Ladder Diagrams for details.
SV READ 2 Section 5-17