TB7100 Service Manual Functional Description 21
© Tait Electronics Limited October 2005
3.1.1 RF Hardware
Front End Circuitry
and First IF
The front-end hardware amplifies and image filters the received RF
spectrum, then down-converts the desired channel frequency to a first
intermediate frequency IF1 of 45.1MHz (UHF) or 21.4MHz (VHF) where
coarse channel filtering is performed. The first LO (local oscillator) signal is
obtained from the frequency synthesizer and is injected on the low side of
the desired channel frequency for all bands. When receiving the modulation
to the frequency synthesizer is muted. The output of the first IF
(intermediate frequency) stage is then down-converted using an image-
reject mixer to a low IF of 64kHz.
Quadrature
Demodulator
The LO for the image-reject mixer (quadrature demodulator) is synthesized
and uses the TCXO (temperature-compensated crystal oscillator) as a
reference. This ensures good centring of the IF filters and more consistent
group-delay performance. The quadrature demodulator device has an
internal frequency division of 2 so the second LO operates at
2 x (IF1 + 64kHz). The quadrature output from this mixer is fed to a pair
of ADCs (analog-to-digital converters) with high dynamic range where it is
oversampled at 256kHz and fed to the custom logic device.
Figure 3.2 Receiver high-level block diagram
IF:
UHF: 45.1 MHz
VHF: 21.4 MHz
Digital
down-
converter
Squelch
Front
end
1st
IF
Channel
LPF
Channel
LPF
RSSI
Second LO
UHF: 90.328 MHz
VHF: 42.928 MHz
FM
Demod
Quad
Demod
RX
AGC
Analogue-to-digital conversion
2nd IF:
64 kHz
Audio
filtering
De-
emphasis
Optional
processing
Data and signalling
decoders
Side
tones
System Interface
or User Interface
Phase
locked to
TCXO
LPF
ANT
Mag.
PLL
Loop
filter
Loop
filter
Frequency
control
Triple-point
Equalisation
TCXO:
13.000 MHz
VCO
VCXO
CUSTOM-
LOGIC
BLOCK
HARDWARE BLOCK
Digital-to-analogue conversion
KEY
NOTES
(1) Noise blanker not shown
DSP
BLOCK
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