Network Synchronization
Page 226 7750 SR OS Basic System Configuration Guide
Central Synchronization Sub-System
The timing subsystem for the SR/ESS platforms has a central clock located on the CPM
(motherboard). The timing subsystem performs many of the duties of the network element clock as
defined by Telcordia (GR-1244-CORE) and ITU-T G.781.
The system can select from up to four timing inputs to train the local oscillator. The priority order
of these references must be specified. This is a simple ordered list of inputs: {bits, ref1, ref2}. The
CPM clock output shall have the ability to drive the clocking for all line cards in the system.
The recovered clock will be able to derive its timing from any of the following:
• OC3/STM1, OC12/STM4, OC48/STM16, OC192/STM64 ports
• T1/E1 CES channel (adaptive clocking)
• Synchronous Ethernet ports
• BITS port on a Channelized OC3/STM1 CES CMA (7710 SR-c4, 7710 SR-c2, and the
7750 SR-c12)
• BITS port on the CPM or CFM module
On 7750 SR-12 and 7750 SR-7systems with redundant CPMs, the system will have two BITS
input ports (one per CPM). These BITS input ports provide redundant synchronization inputs from
an external BITS/SSU. On systems with cross coupled timing modules, the active CPM shall be
capable of using either BITS input port for its synchronization.
All settings of the signal characteristics for the BITS input applies to both ports. When the active
CPM considers the BITS input as a possible reference, it will consider first the BITS input port on
the active CPM followed the BITS input port on the standby CPM in that relative priority order.
This relative priority order is in addition to the user definable ref-order. For example, a ref-order of
‘bits-ref1-ref2’ would actually be BITS in (active CPM) followed by BITS in (standby CPM)
followed by ref1 followed by ref2.
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