Global memory performance features
119
Performance and Optimization
For example, for an instruction requesting to write 256 memory
words of data to a given address, the global memory director will
break out this request into four bursts:
◆ The first 64-word chunk (from 1 to 64) is written to region 1.
◆ The second chunk (from 65 to 128) is written to region 2.
◆ The third chunk (from 129 to 192) is written to region 3.
◆ The last chunk (from 193 to 256) is written to region 4.
Striping of data across the four memory regions on the global
memory directors eradicates any contention for I/O through global
memory.
Tag Based Caching
(TBC)
Enginuity uses Tag Based Caching (TBC) Least Recently Used (LRU)
algorithm for cache management. Enginuity divides global memory
into groups of several hundred slots. In the TBC data structure, four
bytes represent each slot. The four bytes contain information about
the last time the system most recently accessed this slot, whether the
slot is write pending, and other attributes. Each memory slot is
represented by one tag. Tags are clustered into groups called extents.
The TBC LRU algorithm determines which slot in an extent was least
recently used. This TBC LRU slot then loses its association with the
track/data that is stored. Getting a new slot means reading all the
presenting bytes of a TBC extent and choosing the oldest one to be
replaced. Changing one bit removes it from the LRU pool of available
slots. Figure 31 on page 119 illustrates the TBC LRU process.
Figure 31 TBC LRU function
All the CPUs in a Symmetrix system access all the TBC extents.
Enginuity manipulates the TBC extent under lock. To avoid
contention over one TBC extent, each CPU in the Symmetrix system
accesses the TBC extents in a different order, which guarantees even
loads on the different TBC extents at any given time. TBC simplifies
LRU implementation.
…
Each color represents a different “slot age”
Best candidates for replacement
extent 1 extent 2 extent n
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