Emerson PNC001-A Series User Manual

PACSystems™ RX3i and RSTi-EP CPU Reference Manual Section 4
GFK-2222AK October 2019
CPU Operation 98
hardware TOD clock is set with the YYYY: Mon: Day: Hr: Min: Sec fields in the POSIX
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time, the RTC is read, and the delta between the POSIXtime and the value read from the
RTC is computed and saved. Thus, if 1-second resolution is desired the hardware TOD
clock is read. Otherwise, the high-resolution software TOD clock is read to provide
greater resolution. When the latter occurs, the hardware RTC is read and the saved delta
added to the value read.
When the SNTP Time Transfer feature is implemented, all SNTP time updates received at
the CPU will cause the high-resolution software TOD clock to be updated.
4.8.2.2 Synchronizing the High-resolution Time of Day Clock to an
SNTP Network Time Server
In an SNTP system, a computer on the network (called an SNTP server) sends out a
periodic timing message to all SNTP-capable Ethernet Interfaces on the network, which
synchronize their internal clocks with this SNTP timing message. If SNTP is used to
perform network time synchronization, the time-stamp information typically has ±10ms
accuracy between controllers on the same network.
Synchronizing the CPU TOD clock to an SNTP server allows you to set a consistent time
across multiple systems. Once the CPU TOD clock has been synchronized with the SNTP
time, all produced EGD exchanges will use the CPU TOD current value for the time-stamp.
The CPU TOD clock is set with accuracy within ±2ms of the SNTP time-stamp.
TOD clock synchronization is enabled on an Ethernet module by the advanced user
parameter (AUP), ncpu_sync. The CPU must also use a COMMREQ in user logic to select an
Ethernet module as the time master. For additional information, refer to Time-stamping of
Ethernet Global Data Exchanges in PACSystems RX3i and RSTi-EP TCP/IP Ethernet
Communications User Manual, GFK-2224 Section 4.
4.8.3 Watchdog Timer
4.8.3.1 Software Watchdog Timer
A software watchdog timer in the CPU is designed to detect failure to complete sweep
conditions. The timer value for the software watchdog timer is set by using the
programming software. The allowable range for this timer is 10 ms to 2550 ms; the
default value is 200 ms. The software watchdog timer always starts from zero at the
beginning of each sweep.
The software watchdog timer is useful in detecting abnormal operation of the application
program that prevents the CPU sweep from completing within the user-specified time.
Examples of such abnormal application program conditions are as follows:
▪ Excessive recursive calling of a block
▪ Excessive looping (large loop count or large amounts of execution time for each
iteration)
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RSTi-EP CPE100/CPE115 does not allow the Time-of-Day clock to be set older than 1
st
Jan, 2001 when POSIX format is used along with
SVC_REQ 7.

Emerson PNC001-A Series Specifications

General

Brand	Emerson
Model	PNC001-A Series
Category	Controller
Language	English