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Emerson PNC001-A Series User Manual

Emerson PNC001-A Series
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PACSystems™ RX3i and RSTi-EP CPU Reference Manual Appendix A
GFK-2222AK October 2019
Serial I/O, SNP & RTU Protocols 218
DSM314 Sweep Impact
No. of Axes
Configured
Rx3i CPU310 Rack (µs)
Rx3i NIU001+ Rack (µs)
Main
Exp
Main
Exp
1
1535
2160
1830
2360
2
2018
2906
2304
3160
3
2500
6371
2840
3920
4
2990
4430
3350
4680
A-3.11 I/O Interrupt Performance and Sweep Impact
There are several important performance numbers for I/O interrupt blocks. The sweep
impact of an I/O interrupt invoking an empty block measures the overall time of fielding
the interrupt, starting up the block, exiting the block, and restarting the interrupted task.
The time to execute the logic contained in the interrupt block affects the limit by causing
the CPU to spend more time servicing I/O interrupts and thus reduce the maximum I/O
interrupt rate.
The minimum, typical, and maximum interrupt response times reflect the time from
when a single I/O module sees the input pulse until the first line of ladder logic is executed
in the I/O interrupt block. Minimum response time reflects a 300 µs input card filter time
+ time from interrupt occurrence to first line of ladder logic in I/O interrupt block. The
minimum response time can only be achieved when no intelligent option modules are
present in the system and the programmer is not attached. Typical response time is the
minimum response time plus a maximum interrupt latency of 2.0 ms. This interrupt
latency time is valid, except when one of the following operations occurs:
The programmer is attached.
A store of logic, RUN Mode Store, or word-for-word change occurs.
A fault condition (logging of a fault) occurs.
Another I/O interrupt occurs.
The CPU is transferring a large amount of input (or output) data from an I/O
controller (such as a GBC). Heavily loaded I/O controllers should be placed in the
main rack whenever possible.
An event that has higher priority and requires a response occurs. An example of this
type of event is clearing the I/O fault table.
Any one of these events extends the interrupt latency (the time from when the interrupt
card signals the interrupt to the CPU to when the CPU services the interrupt) beyond the
typical value. However, the latency of an interrupt occurring during the processing of a
preceding I/O interrupt is unbounded. I/O interrupts are processed sequentially so that
the interrupt latency of a single I/O interrupt is affected by the duration of the execution
time of all preceding interrupt blocks. (The worst case is that every I/O interrupt in the

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Emerson PNC001-A Series Specifications

General IconGeneral
BrandEmerson
ModelPNC001-A Series
CategoryController
LanguageEnglish

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