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PACSystems™ RX3i and RSTi-EP CPU Reference Manual Section 4

GFK-2222AK October 2019

CPU Operation 79

4.1.1 Parts of the CPU Sweep

There are seven major phases in a typical CPU sweep as shown in the following figure.

Figure 10: Major Phases of a Typical CPU Sweep

Prog

window

scheduled

yes

Communications

Controller

Window

Comm

window

scheduled

yes

Backplane

Communications

Window

Start next sweep

SWEEP

Background

task

scheduled

Background task

Window

yes

Application Program

Task Execution

(Logicwindow)

WINDOW)

Start-of-Sweep

Housekeeping

input scan

Output Scan

Table of Contents3
Table of Figures8
Introduction9
Revisions in this Manual10
Pacsystems Control System Overview13
Programming and Configuration13
Process Systems13
Pacsystems CPU Models14
Rx3I Overview15
Rsti-EP Overview18
Migrating Series 90 Applications to Pacsystems19
Documentation20
Pacsystems Manuals20
Rx3I Manuals20
Field Agent Manuals21
Rsti-EP Manuals21
Series 90 Manuals21
Distributed I/O Systems Manuals21
CPU Features & Specifications23
Common CPU Features23
Features Shared by Certain Pacsystems CPU Models24
Firmware Storage in Flash Memory24
Operation, Protection, and Module Status25
Ethernet Global Data25
Embedded PROFINET Controller25
Figure 1: Configuring an Embedded PROFINET Controller26
Opc Ua27
Removable Data Storage Devices (Rdsds)28
Uploading a Project from the CPU to the RDSD29
Downloading a Project from the RDSD to the CPU30
CPU Over-Temperature Monitoring and Behavior32
Rx3I CPU Features and Specifications34
Rsti-EP CPU Features and Specifications41
Cpe100/Cpe11544
Figure 2: CPE100, Front, Top, and Bottom Views and Features44
Figure 3: CPE100/CPE115 Membrane Pushbutton and Module Status Leds46
Figure 4: State Diagram for CPE100/CPE115 Run/Stop Operation47
Figure 5: Typical Multi-Tier LAN Application (Star/Bus Topology)50
Figure 6: Typical Multi-Tier LAN Application (Ring Topology)50
CPU Configuration53
Configuring the CPU53
Configuration Parameters54
Settings Parameters54
Modbus TCP Address Map58
Sntp59
Time60
Scan Parameters62
Memory Parameters65
Fault Parameters68
Redundancy Parameters (Redundancy Cpus Only)70
Transfer List70
COM1 and COM2 Parameters70
Scan Sets Parameters75
Power Consumption Parameters76
Access Control76
OPC UA Parameters78
Storing (Downloading) Hardware Configuration78
Figure 7: Downloading Hardware Config to CPU78
Configuring the Embedded Ethernet Interface79
Figure 8: Embedded Ethernet Interface Configuration79
Establishing Initial Ethernet Communications80
Setting a Temporary IP Address81
Figure 9: Set Temporary IP Address82
CPU Operation85
CPU Sweep86
Parts of the CPU Sweep87
Figure 10: Major Phases of a Typical CPU Sweep87
CPU Sweep Modes91
Figure 11: Typical Sweeps in Normal Sweep Mode91
Figure 12: Typical Sweeps in Constant Sweep Mode93
Program Scheduling Modes94
Window Modes94
Figure 13: Typical Sweeps in Constant Window Mode94
Data Coherency in Communications Windows95
Run/Stop Operations96
CPU STOP Modes96
Figure 14: CPU Sweep in Stop-I/O Disabled and Stop-I/O Enabled Modes97
STOP-To-RUN Mode Transition99
Flash Memory Operation100
RUN/STOP Switch Operation101
Logic/Configuration Source and CPU Operating Mode at Power-Up101
CPU Mode When Memory Not Preserved/Power-Up Source Is Flash103
CPU Mode When Memory Preserved104
Clocks and Timers105
Elapsed Time Clock105
Time-Of-Day Clock105
Watchdog Timer106
System Security108
Passwords and Privilege Levels - Legacy Mode108
OEM Protection - Legacy Mode112
Enhanced Security for Passwords and OEM Protection113
Legacy/Enhanced Security Comparison115
Pacsystems I/O System116
I/O Configuration117
I/O System Diagnostic Data Collection119
Power-Up and Power-Down Sequences120
Communications127
Ethernet Communications127
Embedded Ethernet Interfaces127
Figure 15: CPE330 Overlapping Local IP Subnet Example128
Figure 16: Expected Response Path130
Figure 17: Actual Response Path130
Ethernet Interface Modules132
Serial Communications132
Serial Port Communications Capabilities133
Configurable STOP Mode Protocols134
Serial Port Pin Assignments134
Figure 18: COM1 Port CPE400/CPL410136
Serial Port Electrical Isolation138
Serial Cable Lengths and Shielding139
Serial Port Baud Rates139
Communications Coprocessor Module (CMM)140
Programmable Coprocessor Module (PCM)140
Serial I/O, SNP & RTU Protocols143
Configuring Serial Ports Using COMMREQ Function 65520143
COMMREQ Function Example143
Timing144
Sending Another COMMREQ to the same Port144
Invalid Port Configuration Combinations144
COMMREQ Command Block Parameter Values144
Figure 19: COMMREQ Example144
Example COMMREQ Command Blocks for Serial Port Setup Function146
Example COMMREQ Command Block for Configuring SNP Protocol146
Example COMMREQ Data Block for Configuring RTU Protocol147
Example COMMREQ Data Block for Configuring Serial I/O Protocol148
Serial I/O Protocol149
Calling Serial I/O Commreqs from the CPU Sweep149
Compatibility149
Status Word for Serial I/O Commreqs150
Serial I/O COMMREQ Commands152
Overlapping Commreqs152
Initialize Port Function (4300)153
Set up Input Buffer Function (4301)154
Flush Input Buffer Function (4302)155
Read Port Status Function (4303)155
Write Port Control Function (4304)158
Cancel COMMREQ Function (4399)159
Autodial Function (4400)161
Write Bytes Function (4401)162
Read Bytes Function (4402)164
Read String Function (4403)165
RTU Slave Protocol167
Message Format168
Figure 20: RTU Message Transactions168
Figure 21: RTU Read Output Table Example171
Cyclic Redundancy Check (CRC)173
Figure 22: CRC Register Operation174
RTU Message Descriptions178
Figure 23: RTU Read Output Table Message Format178
Figure 24: RTU Read Input Table Message Format179
Figure 25: RTU Read Registers Message Format180
Figure 26: RTU Read Analog Inputs Message Format181
Figure 27: RTU Force Single Output Message Format182
Figure 28: RTU Preset Single Register Message Format183
Figure 29: RTU Read Exception Status Message Format184
Figure 30: RTU Loopback/Maintenance Message Format185
Figure 31: RTU Force Multiple Outputs Message Format187
Figure 32: RTU Preset Multiple Registers Message Format188
Figure 33: RTU Report Device Type Message Format189
Figure 34: RTU Read Scratch Pad Memory Message Format194
RTU Scratch Pad195
Communication Errors196
Figure 35: RTU Error Response Format196
RTU Slave/Snp Slave Operation with Programmer Attached198
SNP Slave Protocol199
Permanent Datagrams199
Communication Requests (Commreqs) for SNP200
Appendix A: Performance Data201
A-1.1 Boolean Execution Measurements (Ms Per 1000 Boolean Executions)201
Instruction Timing203
Overview203
A-2.2 Rx3I & Rsti-EP Instruction Times205
A-3 Overhead Sweep Impact Times206
Base Sweep Times206
A-3.2 What the Sweep Impact Tables Contain208
A-3.3 Programmer Sweep Impact Times209
I/O Scan and I/O Fault Sweep Impact210
A-3.5 Ethernet Global Data Sweep Impact215
EGD Sweep Impact for Embedded Ethernet Interface on Rx3I & Rsti-EP CPE Models220
CPE100/CPE115 213 A-3.8 Embedded Ethernet Interface221
Normal Sweep - EGD on Rx3I CPE302/CPE305/CPE310 and Rsti-EP CPE100/CPE115221
Constant Sweep - EGD on Rx3I CPE302/CPE305/CPE310 and Rsti-EP CPE100/CPE115223
Embedded Ethernet Interface223
A-3.10 Sweep Impact of Intelligent Option Modules223
A-3.11 I/O Interrupt Performance and Sweep Impact226
Figure 36: Interrupt Execution Considerations227
Figure 37: Interrupt Execution Considerations227
Timed Interrupt Performance228
A-4 User Memory Allocation229
A-5 Items that Count against User Memory229
A-6 User Program Memory Usage230
A-6.1 %L and %P Program Memory230
A-6.2 Program Logic and Overhead231

Brand	Emerson
Model	PNC001-A Series
Category	Controller
Language	English

Emerson PNC001-A Series User Manual

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