Intel® Server Board S1200V3RP TPS Appendix C: POST Code Diagnostic LED Decoder
Revision 1.2
Memory Initialization at the beginning of POST includes multiple functions, including: discovery,
channel training, validation that the DIMM population is acceptable and functional, initialization
of the IMC and other hardware settings, and initialization of applicable RAS configurations.
When a major memory initialization error occurs and prevents the system from booting with data
integrity, a beep code is generated, the MRC will display a fatal error code on the diagnostic
LEDs, and a system halt command is executed. Fatal MRC error halts do NOT change the state
of the System Status LED, and they do NOT get logged as SEL events. The following table lists
all MRC fatal errors that are displayed to the Diagnostic LEDs.
Table 75. POST Progress LED Codes
No usable memory error
01h = No memory was detected from the SPD read, or invalid
config that causes no operable memory.
02h = Memory DIMMs on all channels of all sockets are disabled
due to hardware memtest error.
3h = No memory installed. All channels are disabled.
Memory is locked by Intel
®
Trusted Execution Technology and is
inaccessible
DDR3 channel training error
01h = Error on read DQ/DQS (Data/Data Strobe) init
02h = Error on Receive Enable
3h = Error on Write Leveling
04h = Error on write DQ/DQS (Data/Data Strobe
Memory test failure
01h = Software memtest failure.
02h = Hardware memtest failed.
03h = Hardware Memtest failure in Lockstep Channel mode
requiring a channel to be disabled. This is a fatal error which
requires a reset and calling MRC with a different RAS mode to
retry.
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