Intel S1200V3RP Technical Product Specification

Functional Architecture Intel® Server Board S1200V3RP TPS
Revision 1.2
18
product family board is set at 10 events. When the 10
th
CE occurs, a single Correctable Error
event is logged.
3.3.3 Post Error Codes
The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST,
this same range of POST code values is used for reporting other system errors.
 0xE8 - No Usable Memory Error: If no usable memory is available, the BIOS emits a
beep code and displays POST Diagnostic LED code 0xE8 and halts the system.
This can also occur if all memory in the system fails and/or has become disabled during
memory initialization. For example, if a DDR3 DIMM has no SPD information, the BIOS
treats the DIMM slot as if no DDR3 DIMM is present on it. Therefore, if this is the only
DDR3 DIMM installed in the system, there is no usable memory, and the BIOS goes to a
memory error code 0xE8 as described above.
 0x53/0x55/0XE8: DIMM SPD does not respond or DIMM SPD Read Error, the DIMM will
not be detected, if the SPD does not respond, which could result in No memory Installed
or No Usable Memory Error Halt 0X53, 0x55, or 0xE8, or could result later in an invalid
configuration if the no SPD DIMM is in Slot 1 on the channel.
 0x51 – Memory SPD Error: If the DIMM does respond but the SPD cannot be
successfully read, that would cause a Memory SPD Error, memory error halt 0X51. For
each memory channel, once the DIMM SPD parameters have been read, they are
checked to verify that the DIMMs on the channel are a valid configuration, DIMM speed
and size, ECC capability, and in which memory slot the DIMMs are installed. An invalid
configuration will cause the system to halt.
 0xEA - Channel Training Error: If the memory initialization process is unable to
properly perform the Data/Data Strobe timing training on a memory channel, the BIOS
emits a beep code and displays POST Diagnostic LED code 0xEA momentarily during
the beeping. If there is usable memory in the system on other channels, POST memory
initialization continues. Otherwise, the system beeps and halts with POST Diagnostic
LED code 0xEA staying displayed.
 0x54/0xEB - Memory Test Error: If a DDR3 DIMM or a set of DDR3 DIMMs on the
same memory channel fails memory testing but usable memory remains available, the
BIOS emits a beep code and displays POST Diagnostic LED code 0xEB momentarily
during the beeping, then continues POST. If all of the memory fails memory testing, then
system memory error code 0xE8 (No Usable Memory) as described above.
 0xED - Population Error or Invalid DIMM: If the installed memory contains an invalid
DIMM configuration on any channel in the system, the system beeps and halts with
POST Diagnostic LED code 0xED. The DIMM are installed incorrectly, not following the
Fill Farthest First rule (Slot 1 must be filled before Slot 2). This will result in a DIMM
Population Error, with a Memory Error Halt 0xED.
3.3.4 Processor Integrated I/O Module (IIO)
The processor’s integrated I/O module provides features traditionally supported through chipset
components. The integrated I/O module provides the following features:
 PCI Express* Interfaces
The integrated I/O module incorporates the PCI Express* interface and supports up to
16 lanes of PCI Express*. Following are key attributes of the PCI Express* interface:

Intel S1200V3RP Specifications

General

Brand	Intel
Model	S1200V3RP
Category	Server Board
Language	English