Platform Management ArchitectureIntel® Server Board SE7520BD2 Technical Product Specification
110 Revision 1.3
4.6.8 Interrupts
The module can receive interrupt events on the pins assigned to XINTx inputs. Two of the
XINTs available on the Sahalee are used internally by the KVM and the private NIC function
associated with the KVM. XINT2 is available for use by an interrupting event.
4.6.9 GPIO Pins and LED Drivers
Many of the external pins of the FMM integrated peripheral devices can be alternatively used as
programmatically controlled general-purpose I/O pins. The pin states (inputs) can be read at all
times. The output source function is selected via mux control that selects between the
peripheral and general purpose I/O (GPIO) functions at the I/O ring.
The GPIO-enabled output buffers can be configured for either totem pole or open-drain
operation. A weak pull-up (minimum value of 12K ohm, maximum value of 48K ohm) connected
to digital VDD is incorporated in each of these buffers. The power-up default of these pins is the
GPIO function configured as an open-drain output in high-impedance mode. The functionality of
the GPIO pins is unaltered by a FMM reset. All FMM signal pins are 5V tolerant, as long as the
two VDD 5V pins are connected to a 5V power supply. The FMM contains seven LED drive
level (12 mA sink current at 0.4 V, 12 mA source current at 2.8 V) output buffers.
4.6.10 Sleep States Supported
The ICH5-R controls the system sleep states. States S0, S1, S4 and S5 are supported. Either
the BIOS or an operating system invokes the sleep states. This is done in response to a power
button being pressed or an inactivity timer countdown. Normally the operating system
determines which sleep state to transition into. However a 4-second power button over-ride
event places the system immediately into S5. When transitioning into a software-invoked sleep-
state, the ICH5-R will attempt to gracefully put the system to sleep by first going into the CPU
C2 state.
4.6.10.1 S0 State
This is the normal operating state, even though there are some power savings modes in this
state using CPU Halt and Stop Clock (CPU C1 and C2 states). S0 affords the fastest wake up
response time of any sleep state because the system remains fully powered and memory is
intact.
4.6.10.2 S1 State
The S1 state is entered via a CPU Sleep signal from the ICH5-R (CPU C3 state). The system
remains fully powered and memory contents remain intact, but the CPUs enter their lowest
power state. The operating system uses ACPI drivers to disable bus masters for uni-processor
configurations, while the operating system flushes and invalidates caches before entering this
state in multiprocessor configurations. Wake latency is slightly longer in this state than S0,
however power savings are quite improved from S0.
4.6.10.3 S2 State
The S2 state is not supported.
4.6.10.4 S3 State
The S3 state is called Suspend to RAM (STR). It is not supported.
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