Intel® Server Board SE7520BD2 Technical Product Specification Error Reporting and Handling
Revision 1.3 Intel Confidential
115
5. Error Reporting and Handling
5.1 Error Propagation
When errors are encountered during POST, error messages or codes are either displayed to the
video screen, or if prior to video initialization, reported through a series of audio beep codes.
The error codes are defined by Intel and whenever possible are backward compatible with error
codes used on earlier platforms.
5.2 Fault Resilient Booting (FRB)
5.2.1 FRB-3 – BSP Reset Failures
The BIOS and firmware provide a feature to guarantee that the system boots, even if one or
more processors fail during POST. The BMC contains two watchdog timers that can be
configured to reset the system upon time-out. The first timer (FRB-3) starts counting down
whenever the system comes out of hard reset. If the BSP successfully resets and begins
executing, the BIOS disables the FRB-3 timer in the BMC and the system continues executing
POST. If the timer expires because of the BSP’s failure to fetch or execute BIOS code, the BMC
resets the system and disables the failed processor. The BMC continues to change the
bootstrap processor until the BIOS successfully disables the FRB-3 timer. The BMC sounds
beep codes on the system speaker if it fails to find a good processor. It will continue to cycle
until it finds a good processor. The process of cycling through all the processors is repeated
upon system reset or power cycle. Soft resets do not affect the FRB-3 timer. The duration of
the FRB3 timer is set by system firmware.
5.2.2 FRB-2 – BSP POST Failures
The second timer (FRB-2) is set to several minutes by BIOS and is designed to guarantee that
the system completes POST. The FRB-2 timer is enabled just before the FRB-3 timer is
disabled to prevent any “unprotected” window of time. Near the end of POST, the BIOS disables
the FRB-2 timer. If the system contains more than 1 GB of memory and the user chooses to test
every DWORD of memory, the watchdog timer is extended before the extended memory test
starts, because the memory test can exceed the timer duration. The BIOS will also disable the
watchdog timer before prompting the user for a boot password. If the system hangs during
POST, before the BIOS disables the FRB-2 timer, the BMC generates an asynchronous system
reset (ASR). The BMC retains status bits that can be read by the BIOS later in the POST for the
purpose of disabling the previously failing processor, logging the appropriate event into the
System Event Log (SEL), and displaying an appropriate error message to the user.
Options are provided by the BIOS to control the policy applied to FRB-2 failures. By default, an
FRB-2 failure results in the failing processor being disabled during the next reboot. This policy
can be overridden to prevent BSP from ever being disabled due to the FRB-2 failure or a policy
resulting in disabling the BSP after three consecutive FRB-2 failures can be selected. These
options may be useful in systems that experience fatal errors during POST that are not
indicative of a bad processor. Selection of this policy should be considered an advanced
feature and should only be modified by a qualified system administrator. If supported by the
specific platform, these options can be found in BIOS Setup.
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