Theory
of
operation-PS
50
10
base of the pass-transistor is controlled by ORing the out-
puts of the voltage and current loops through appropriate
drodes. There is no fold-back circuitry for this supply as the
voltage in the current mode can range from
0 to the set
value. Since the supply is floating, information for the cur-
rent and voltage digital-to-analog converters pass through
an optical isolation link. The balance status comparator in-
formation to the CPU board also passes through an optical
isolation link.
The floating supplies utilize remote sensing. There are
three remote sensing lines,
+
supply,
-
supply, and com-
mon. In front-panel operation, the
+
sense is connected to
the POSITIVE, the common to the common, and the nega-
tive sense to the NEGATIVE front-panel connectors. In rear
interface operation, the sense lines and the output lines are
separate.
The positive voltage digital-to-analog converter is
referenced to the common sense line. One input of the volt-
age error amplifier is also referenced to the same point. The
negative
output voltage from the voltage DAC is summed
with the positive output voltage on the sense line, and the
difference signal is fed to the other input of the voltage error
amplifier. The output of the voltage error amplifier is diode
ORd with the current amplifier and also connects to the loop
balance status comparator.
The
+
current DAC is referenced to COMMON for the
supply. The negative output voltage from the current DAC is
summed with the voltage across the sense resistor and the
difference signal is fed to the other input of the current error
amplifier and added to the voltage output from the
-k
cur-
rent DAC. The current across the sense resistor is equal to
the output current of the supply. The output of the current
error amplifier is
ORd to the base of the series pass-transis-
tor and also provides a signal that passes to the loop bal-
ance status comparator.
The current through the emitter of the pass-transistor
passes through the output relay and the input-output select
switch to the selected output terminal.
DETAILED CIRCUIT DESCRIPTION
The GPlB communications are controlled by U1001,
U 1000, and U1010. Bidirectional buffers U1000 and U1010
provide drive capability for U1001, the GPlB interface. The
IEEE 488-1975178 standard protocol is handled automati-
cally in both talker and listener modes by U1001. This in-
strument is assigned a 5 bit address to enable talker or
listener addressing over the bus. This address is set on
switch
S1221 shown on schematic 4. The switch is located
on the CPU board (A12). The switch settings are read by the
microprocessor at power on and written into the address
register of U 1 001.
CPU
Regulator
0
Voltage comparator U1020A and the series pass-transis-
tor Q1021 furnish the +5 V power to the Logic Supply Filter
board, A1
3,
Front-Panel board, A1
0,
and CPU board, A1
2.
When the current through the sense resistor R1018 is about
1.8 A, transistor 01 020 reduces base drive to Q1021. This
provides foldback curent limiting. The foldback current limit
is 0.6 A at 0
V.
The output of the voltage comparator
U1020A is ORd with the output of the current foldback
Q1020 through CR1020. Reference voltage (5 V) is pro-
vided by Zener diode
VR1011.
When the mainframe supply voltages are stable. the
PWR line is TTL high. This PWR signal from the mainframe
is applied to the
+
input of U1020B. This comparator pro-
vides signal hysteresis at
+
0.7
V
to
+
2 V to eliminate the
effects of noise on the PWR line. The output of U10206 at
pin
7
is delayed about 10 ms by R1125 and C1120. This
signal is compared to the 5
V
reference on the
+
input of
U1020C. IC U1020C drives (21125, providing the open
collector PON signal to the microprocessor.
The power on reset RES, for the processor and related
circuitry, is the
PON
signal ANDed with Ext Reset.
Microprocessor
The M6800 microprocessor, Ul 1 1 1, controls the internal
operation of the PS 5010. It accepts commands from either
the front panel or GPIB. It sets the operating parameters in
response to these commands. The M6800 is an 8 bit parallel
processor with a 16 bit address bus. The data bus
IS
buffered by U1202 and the lower 8 address lines.
A0
through
A7,
are buffered by U1210.
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