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After the computer has transmitted all
of
the data and address information to the VDT controller,
the computer issues a Write Data Strobe
on
the data line (with module select, four-bit CRU address,
and clock). The VDT controller responds by storing the screen data code into its refresh memory
at the cursor address provided by the computer. The VDT controller also encodes the computer-
provided data into dot patterns to be transmitted to the CRT monitor for display.
For
each
character
to
be displayed on the CRT screen, the VDT controller produces
10
(
16
for 960-character
display) seven-dot codes (one for each
of
the 10 scan lines required for each character block on the
screen). The controller generates timing signals to provide horizontal and vertical synchronization
signals for the CRT monitor and superimposes them on the video data signal
to
produce a com-
posite video signal for the CRT monitor.
During normal typing operations where screen data
is
repeatedly transferred from the keyboard
to the computer and back
to
the CRT monitor, the computer provides the VDT controller with
the initial cursor address and a control bit that causes the VDT controller
to
increment the
cursor address for each succeeding transfer. A cursor address counter in the VDT controller
performs the incrementing so that all characters are transmitted in the proper order and stored in
refresh memory in consecutive locations.
For
operations other than transmission
of
information
for display in consecutive lpcations, the computer provides an 11-bit cursor address for each
character
to
be displayed.
The VDT controller provides a software alarm function for the computer. The controller
produces a signal
that
enables an oscillator in the display unit cabinet in response
to
CRU
output
bit E
16
(bit F
16
=
1)
from the computer (transferred over the serial
output
data line
as
previously described). The signal can be used to indicate the entry
of
illegal codes and other
software violations.
The computer can direct the VDT controller to enter the self-test mode. In the self-test mode,
the computer monitors the root signals
of
outputs to the VDT and simulates keyboard input
from the VDT. Diagnostic software examines these signals
to
verify timing and for fault
isolation. The computer accomplishes this operation by setting
five
control bits on the controller
interface
to
direct the
VDT
controller to return simulated keyboard data, video, horizontal sync,
vertical sync, and audio signals. Simulated keyboard data
is
one
of
four patterns
as
determined
by two control bits. Only one
of
the four inputs (video, horizontal sync, vertical sync
or
audio)
is
available during self-test and
is
selected by two control bits.
1.3 INTERFACE DESCRIPTIONS
The following paragraphs describe the interfaces between the VDT controller and the computer,
the keyboard and the power/logic pwb, the power/logic pwb and the VDT controller, and the
power/logic pwb and the CRT monitor.
1.3.1 VDT CONTROLLER/COMPUTER INTERFACE. The interface between the VDT con-
troller and the computer
is
illustrated in figure
1-5.
The interface
is
the serial CRU interface
of
the Model 990 family
of
computers. The CRU interface provides for up
to
4096 directly
addressable input bits and up
to
4096 directly addressable
output
bits. The VDT controller/
computer interface utilizes
16
directly addressable bits each for input and output operations for
each controller resident on the VDT controller pwb. Computer operations can address the bits
individually
or
in fields
of
from one
to
16
bits. The computer instructions that drive the CRU
interface can set, reset, or test any bit on the interface
or
move data between computer memory
and the CRU data fields. These
16
directly addressable bits are multiplexed to effectively provide
3 2 input and 3 2
output
signals.
CRU operations can be divided into two broad categories: those involving a single control bit
transfer and those requiring input or
output
of
multiple data or status bits.
1-9
Digital
Systems Division
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