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945424-9701
With
no
composite sync signal present,
as
would be
the
case
if
the
video display
unit
were
not
connected
to
a VDT controller,
the
timer
provides an artificial horizontal sync signal
to
be used
for self-test. The
horizontal
synchronization signal,
whethci
prnvidcd
by
the
VDT controller
or
generated
at
the
"natural"
frequency
of
the
timer
network,
clocks all operations
of
the
UART.
_ . _
~-
,
--
- • - . • • • • • , , •
.._
_
..
_
~
___
1
"'T"'1-
_ T
T:1'
!-
.LL. - C" T
L'T'\.
The
Sync (S) LED contmua!!y !lghts
when
power
1s
appnea
rn
me
rerrnmai.
int:
LDu
1:s
we..-,
Leu
shown
in
figure 1-24. Terminal Ready (signals
TRD
1 T = logic 0
and
TRD2T
= logic 1) indicates
the
terminal
is
powered
on
and
does
not
depend
upon
any
controller
input.
1.4.2.10
Audio Circuitry. Figure 1-29 illustrates
the
circuitry
that
monitors
Beep Enable from
the
VDT controller
and
audio from an external
modem
(relayed
by
the
VDT controller).
The
differential (two-wire) line receiver for Beep Enable provides noise
immunity.
The
software alarm
condition
(Beep Enable) enables
the
SN74LS132
to
oscillate
at
a frequency determined
by
the
time
constant
of
the
RC biasing network.
The
SN74LSOO isolates
the
Beep Enable
input
circuitry from
the
modem
audio
input.
The
LM386N amplifies whatever
input
it
is provided
(Beep Enable-produced oscillator
output
or
modem
audio) and provides
the
amplified audio
signal
to
a loudspeaker
and
volume
control
mounted
in
the
front
portion
of
the
display
unit's
base.
1.4.3
CRT
MONITOR. Figure 1-30
is
a
block
diagram
of
the
CRT
monitor
located
in
the
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'-'.I.
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•
The
video amplifier amplifies
the
video
data
received
from
the
power/logic
pwb
and modulates
the
cathode
of
the
CRT. A BRIGHTNESS
control
adjusts
the
brightness
of
the
display
by
varying
the
relative
de
potential
between
the
CRT
cathode
and
the
control
grid.
The
horizontal amplifier, triggered
by
horizontal
drive pulses, develops a
sawtooth
current
to
drive
the
horizontal deflection coils
of
the
CRT yoke.
The
horizontal deflection circuit drives
the
horizontal
coils and
the
flyback circuits
to
develop high voltage for
the
second anode,
de
voltages
fOi
CRT bias (fiist anode), focus and accelernting grids and a de voltage for
the
video
output
stage.
The
vertical amplifier is triggered
by
the
vertical synchronization pulses from
the
power/logic
pwb
and develops
the
SO-hertz
or
60-hertz
sawtooth
currents used
to
drive
the
vertical deflection
coils
of
the
CRT
yoke.
1.4.4
VDT
CONTROLLER.
A
block
diagram
of
the
VDT controller is
shown
in
figure 1-31.
The
controller
is
implemented
on
a full-size
CRU
pwb
that
is installed
into
a designated
backpanel slot in
either
the
main
computer
chassis
or
an expansion chassis. The VDT controller
performs
the
following functions:
• Provides
data
paths
between keyboard and
computer
and
between
computer
and
CRT
monitor
• Generates video format character codes for
96
standard display symbols including
uppercase and lowercase alphabet characters, numeric characters, and special symbols
(+,
-,
;,
etc.)
1-44
Digital
Systems Division
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