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1.4.4.8 Time Base Generator. The time base
generator
produces all
the
signals necessary for
timing and synchronizing VDT controller operations. Figures 1-49 and 1-50 illustrate
the
logic
that
makes
up
the
time base generator.
NOTE
A dual-controller VDT contrnller contains only one time base
generator
that
provides identical functions for
both
controllers
on
the P'Nb.
Oscillator. The oscillator is a monolithic crystal oscillator circuit with crystal, oscillator circuit,
and
TTL
output
buffer
in a single 14-pin package. The crystal is
cut
for 11.004 megahertz.
Clock Buffer/Selector. The clock buffer/selector selects
the
output
of
the crystal oscillator
(PHI)
or
an externally-produced clock (EXTCLOCK) for use
by
VDT controller logic. Grounding CEL
disables
the
crystal oscillator so
that
an external clock
may
be used. Leaving CEL ungrounded
enables
the
oscillator and disables
the
external clock (EXTCLK).
The basic clock period
of
90
nanoseconds determines
the
size
of
elements
within
a displayed
character
matrix.
For
example, alphanumeric characters are five
dots
across and seven
dots
high.
High-intensity character dots are a full 90-nanosecond
dot
period, and low-intensity characters
are 45-nanosecond half-dot period.
Dot
Counter. The
dot
counter
divides
the
11.004-megahertz clock (CLK)
into
seven 1.57-megahertz
clocks used
to
synchronize events
throughout
the
controller. Figure 1-51 illustrates
the
relationship
between CLK and
the
seven 1.57-megahertz
dot
clocks. The
counter
forces zeros
into
the
serial
input
of
a shift register until
the
first six
outputs
(DOTRO
through
DOTRS) are zero.
Then
the
counter
enables a I
to
the
shift register
input
(DOTR6= I) and
the
next
CLK drives DOTRO
to
1.
Interval
limers.
The interval
timer
flip-flops produce
two
1.57-megahertz
outputs
(D2TRUSQ
and D2TRU6Q). D2TRU5Q controls memory write enable.
D2TRU6Q
gates
memory
addresses
and enables the
output
of
the
graphic character generator during lines 8 and 9, and
the
standard
character generator during lines 0 through
7.
Character Counter and Character Address Counter. The character
counter
and character address
counter
count
the
number
of
character positions (0-99) for each scan line and
count
the
character positions as the
CRT
screen is scanned. Following are specific character address counts
for
the
character address counter:
Character
Firsi displayed character
960th character or 960-character screen
1920th character on 1920-character screen
Count
0
3BF16
77F16
The
maximum
allowable
count
of
FFF
16
is never reached because
the
counter
is reset to 0 at
the
end
of
a frame. Figures
1-5
2 and 1-53 illustrate
the
counting scheme for 960- and 1920-
character displays, respectively.
1-62
Digital
Systems Division
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