KCU105 Board User Guide www.xilinx.com 118
UG917 (v1.4) September 25, 2015
Appendix D
Master Constraints File Listing
Overview
The master Xilinx design constraints (XDC) file template for the KCU105 board provides for
designs targeting the KCU105 evaluation board. Net names in the constraints listed
correlate with net names on the latest KCU105 evaluation board schematic. Users must
identify the appropriate pins and replace the net names with net names in the user RTL. See
the Vivado Design Suite User Guide: Using Constraints (UG903) [Ref 16] for more
information.
For detailed I/O standards information required for a particular interface, refer to the
constraint files generated by tools such as the memory interface generator (MIG) and base
system builder (BSB).
The FMC connectors J2 (LPC) and J22 (HPC) are connected to 1.8V VADJ banks. Because
different FMC cards implement different circuitry, the FMC bank I/O standards must be
uniquely defined by each customer.
IMPORTANT: The XDC file can be accessed on the KCU105 Evaluation Kit website.
KCU105 Board Constraints File Listing
#CLOCKS
set_property ODT RTT_48 [get_ports "SYSCLK_300_N"]
set_property PACKAGE_PIN AK16 [get_ports "SYSCLK_300_N"]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "SYSCLK_300_N"]
set_property PACKAGE_PIN AK17 [get_ports "SYSCLK_300_P"]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "SYSCLK_300_P"]
set_property ODT RTT_48 [get_ports "SYSCLK_300_P"]
set_property IOSTANDARD LVDS_25 [get_ports "USER_SI570_CLOCK_N"]
set_property PACKAGE_PIN M26 [get_ports "USER_SI570_CLOCK_N"]
set_property IOSTANDARD LVDS_25 [get_ports "USER_SI570_CLOCK_P"]
set_property PACKAGE_PIN M25 [get_ports "USER_SI570_CLOCK_P"]
set_property PACKAGE_PIN G10 [get_ports "CLK_125MHZ_P"]
set_property IOSTANDARD LVDS [get_ports "CLK_125MHZ_P"]
set_property PACKAGE_PIN F10 [get_ports "CLK_125MHZ_N"]
set_property IOSTANDARD LVDS [get_ports "CLK_125MHZ_N"]
set_property PACKAGE_PIN C23 [get_ports "USER_SMA_CLOCK_N"]
To Next Page
General
