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Xilinx RocketIO User Manual
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RocketIO™
T
ransc
eiver User Guide
UG024 (v3.0) F
ebruar
y 22, 2007
Chapter 3:
Analog Design Considerations
R
Figure 3-10
:
Example Po
wer Filtering PCB Lay
out for Four MGTs, In De
vice with
External C
apacito
rs, T
op Layer
P
r
oduc
t
N
o
t
Re
co
m
m
en
d
ed
f
o
r
New
Desig
n
s
113
115
Table of Contents
Default Chapter
1
User Guide
1
Table of Contents
7
Schedule of Figures
13
Schedule of Tables
15
Preface: about this Guide
17
Rocketio Features
17
Guide Contents
17
For more Information
18
Additional Resources
18
Conventions
19
Port and Attribute Names
19
Typographical
19
Online Document
20
Chapter 1 : Rocketio Transceiver Overview
21
Basic Architecture and Capabilities
21
Rocketio Transceiver Instantiations
23
HDL Code Examples
23
List of Available Ports
24
Primitive Attributes
29
Modifiable Primitives
34
Byte Mapping
38
Chapter 2: Digital Design Considerations
39
Clocking
39
Clock Signals
39
Brefclk
41
Clock Ratio
42
Digital Clock Manager (DCM) Examples
42
Example 1A: Two-Byte Clock with DCM
43
Example 1B: Two-Byte Clock Without DCM
46
Example 2: Four-Byte Clock
46
Example 3: One-Byte Clock
50
Half-Rate Clocking Scheme
54
Multiplexed Clocking Scheme with DCM
55
Multiplexed Clocking Scheme Without DCM
55
Rxrecclk
56
Clock Dependency
56
Data Path Latency
57
Reset/Power down
57
8B/10B Encoding/Decoding
60
Overview
60
8B/10B Encoder
60
8B/10B Decoder
60
Ports and Attributes
61
Txbypass8B10B, Rx_Decode_Use
61
Txchardispval, Txchardispmode
62
Txcharisk
63
Txrundisp
63
Txkerr
63
Rxcharisk, Rxrundisp
63
Rxdisperr
64
Rxnotintable
64
Vitesse Disparity Example
64
Transmitting Vitesse Channel Bonding Sequence
64
Receiving Vitesse Channel Bonding Sequence
65
8B/10B Bypass Serial Output
65
8B/10B Serial Output Format
66
HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
66
SERDES Alignment
67
Overview
67
Serializer
67
Deserializer
67
Ports and Attributes
67
Align_Comma_Msb
67
Enpcommaalign, Enmcommaalign
68
Rocketio™ Transceiver User Guide Www.xilinx.com
69
Pcomma_Detect
70
Mcomma_Detect
70
Comma_10B_Mask
70
Pcomma_10B_Value
70
Mcomma_10B_Value
70
Dec_Mcomma_Detect Dec_Valid_Comma_Only
70
Rxrealign
70
Dec_Pcomma_Detect
71
Dec_Mcomma_Detect
71
Dec_Valid_Comma_Only
71
Rxchariscomma
71
Rxcommadet
71
Clock Recovery
71
Overview
71
Clock Synthesizer
71
Clock and Data Recovery
72
Clock Correction
72
Ports and Attributes
73
Clk_Correct_Use
73
Rx_Buffer_Use
74
Clk_Cor_Seq_
74
Clk_Cor_Seq_Len
75
Clk_Cor_Insert_Idle_Flag
75
Clk_Cor_Keep_Idle
75
Clk_Cor_Repeat_Wait
75
Synchronization Logic
76
Overview
76
Ports and Attributes
76
Rxclkcorcnt
76
Rx_Los_Invalid_Incr Rx_Los_Threshold
77
Rx_Los_Threshold
78
Channel Bonding (Channel Alignment)
79
Overview
79
Channel Bonding (Alignment) Operation
80
Ports and Attributes
81
Chan_Bond_Mode
81
Enchansync
81
Chan_Bond_One_Shot
81
Chan_Bond_Seq_
81
Chan_Bond__Seq_Len
81
Chan_Bond_Seq_2_Use
81
Chan_Bond_Wait
82
Chan_Bond_Offset
82
Chan_Bond_Limit
82
Chbonddone
83
Chbondi, Chbondo
83
Rxclkcorcnt, Rxlossofsync
83
Troubleshooting
83
CRC (Cyclic Redundancy Check)
84
Overview
84
CRC Operation
84
CRC Generation
84
CRC Latency
85
Ports and Attributes
85
Tx_Crc_Use
85
Rx_Crc_Use
85
Crc_Format
85
Crc_Start_Of_Packet
88
Crc_End_Of_Packet
88
Rxcheckingcrc, Rxcrcerr
88
Txforcecrcerr, Tx_Crc_Force_Value
89
Rocketio CRC Support Limitations
89
Fabric Interface (Buffers)
89
Overview: Transmitter and Elastic (Receiver) Buffers
89
Transmitter Buffer (FIFO)
89
Receiver Buffer
89
Ports and Attributes
90
Txbuferr
90
Tx_Buffer_Use
90
Rxbufstatus
90
Rx_Buffer_Use
90
Miscellaneous Signals
90
Tx_Data_Width
90
Serdes_10B
90
Termination_Imp
91
Rxpolarity Txinhibit
91
Tx_Diff_Ctrl Pre_Emphasis
91
Loopback
91
Other Important Design Notes
93
Receive Data Path 32-Bit Alignment
93
Bit Alignment Design
95
Verilog
95
Vhdl
98
Chapter 3 : Analog Design Considerations
103
Serial I/O Description
103
Pre-Emphasis Techniques
104
Rocketio™ Transceiver User Guide Www.xilinx.com
105
Differential Receiver
107
Jitter
107
Clock and Data Recovery
108
PCB Design Requirements
109
Power Conditioning
109
Voltage Regulator Selection and Use
109
Termination Voltage
110
Passive Filtering
111
High-Speed Serial Trace Design
115
Routing Serial Traces
115
Differential Trace Design
116
AC and DC Coupling
117
Reference Clock
119
Epson EG-2121CA 2.5V (LVPECL Outputs)
119
Pletronics LV1145B (LVDS Outputs)
119
Powering the Rocketio Transceivers
120
Other Important Design Notes
120
Pin Connections on the Unused Rocketio Transceivers
120
The POWERDOWN Port
120
Chapter 4 : Simulation and Implementation
121
Simulation Models
121
Smartmodels
121
Hspice
121
Implementation Tools
121
MGT Package Pins
123
Appendix A: Rocketio Transceiver Timing Model
129
Timing Parameters
129
Setup/Hold Times of Inputs Relative to Clock
129
Clock to Output Delays
129
Clock Pulse Width
130
Timing Parameter Tables and Diagram
130
Appendix B: 8B/10B Valid Characters
135
Valid Data Characters
135
Valid Control Characters (K-Characters)
143
Appendix C: Related Online Documents
145
Application Notes
145
Serial Interfaces
145
XAPP648: Serial Backplane Interface to a Shared Memory
145
XAPP649: SONET Rate Conversion in Virtex-II Pro Devices
146
XAPP651: SONET and OTN Scramblers/Descramblers
146
XAPP652: Word Alignment and SONET/SDH Deframing
146
And Differential Swing Control Attributes
146
XAPP661: Rocketio Transceiver Bit-Error Rate Tester
147
XAPP662: In-Circuit Partial Reconfiguration of Rocketio Attributes
147
Rocketio Transceivers
147
Rocketio Transceiver
148
Transceivers
148
Multi-Gigabit Transceivers
148
Multi-Gigabit Transceivers
149
XAPP687: 64B/66B Encoder/Decoder
149
XAPP756: Transmitting DDR Data between LVDS and Rocketio CML Devices
149
XAPP763: Local Clocking for MGT RXRECCLK in Virtex-II Pro Devices
149
Characterization Reports
149
Virtex-II Pro Rocketio Multi-Gigabit Transceiver
149
Characterization Summary
150
Virtex-II Pro Rocketio MGT HSSDC2 Cable Characterization
150
White Papers
150
WP157: Usage Models for Multi-Gigabit Serial Transceivers
150
Embedded Rocketio Transceivers
151
Index
153
4
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Xilinx RocketIO Specifications
General
Brand
Xilinx
Model
RocketIO
Category
Transceiver
Language
English
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