Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 13
UG024 (v3.0) February 22, 2007
Chapter 1: RocketIO Transceiver Overview
Figure 1-1: RocketIO Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 2: Digital Design Considerations
Figure 2-1: REFCLK/BREFCLK Selection Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 2-2: Two-Byte Clock with DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 2-3: Two-Byte Clock without DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 2-4: Four-Byte Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 2-5: One-Byte Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 2-6: One-Byte Data Path Clocks, SERDES_10B = TRUE . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-7: Two-Byte Data Path Clocks, SERDES_10B = TRUE . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-8: Four-Byte Data Path Clocks, SERDES_10B = TRUE . . . . . . . . . . . . . . . . . . . . . 54
Figure 2-9: Multiplexed REFCLK with DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-10: Multiplexed REFCLK without DCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2-11: Using RXRECCLK to Generate RXUSRCLK and RXUSRCLK2. . . . . . . . . . 56
Figure 2-12: 8B/10B Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 2-13: 10-Bit TX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 2-14: 10-Bit RX Data Map with 8B/10B Bypassed . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 2-15: 8B/10B Parallel to Serial Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-16: 4-Byte Serial Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 2-17: Synchronizing Comma Align Signals to RXRECCLK . . . . . . . . . . . . . . . . . . 68
Figure 2-18: Top MGT Comma Control Flip-Flop Ideal Locations . . . . . . . . . . . . . . . . . . 69
Figure 2-19: Bottom MGT Comma Control Flip-Flop Ideal Locations . . . . . . . . . . . . . . . 69
Figure 2-20: Clock Correction in Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 2-21: RXLOSSOFSYNC FSM States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 2-22: Channel Bonding (Alignment) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 2-23: CRC Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 2-24: USER_MODE / FIBRE_CHAN Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 2-25: Ethernet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-26:
In
finiband Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2-27: Local Route Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 2-28: Serial and Parallel Loopback Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 2-29: RXDATA Aligned Correctly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 2-30: Realignment of RXDATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Chapter 3: Analog Design Considerations
Figure 3-1: Differential Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 3-2: Alternating K28.5+ with No Pre-Emphasis. . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Schedule of Figures
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English