Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 55
UG024 (v3.0) February 22, 2007
Clocking
R
Multiplexed Clocking Scheme with DCM
Following configuration of the FPGA, some applications might need to change the
frequency of its REFCLK depending on the protocol used. Figure 2-9 shows how the
design can use two different reference clocks connected to two different DCMs. The clocks
are then multiplexed before input into the RocketIO transceiver.
User logic can be designed to determine during auto negotiation if the reference clock used
for the transceiver is incorrect. If so, the transceiver must then be reset and another
reference clock selected.
Multiplexed Clocking Scheme without DCM
As with “Example 1b: Two-Byte Clock without DCM”, the DCMs shown in Figure 2-9 may
be removed if TXDATA and RXDATA are not clocked off the FPGA. (See Figure 2-10.)
However, the transceiver must still be reset when clocks are switched.
Figure 2-9: Multiplexed REFCLK with DCM
REFCLKSEL
GT_std_2
REFCLK
REFCLK2
REFCLKSEL
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
CLKIN
CLKFB
RST
DCM
CLK0
CLK0
BUFGMUX
CLKIN
CLKFB
RST
DCM
0
1
Use of 2 DCMs is required
to maintain correct
IBUFG/DCM/BUFGMUX topology
for clock skew compensation
UG024_05a_112202
REFCLK_P
IBUFGDS
REFCLK_N
REFCLK2_P
REFCLK2_N
Figure 2-10: Multiplexed REFCLK without DCM
REFCLKSEL
GT_std_2
REFCLK
REFCLK2
REFCLKSEL
TXUSRCLK2
RXUSRCLK2
TXUSRCLK
RXUSRCLK
0
1
UG024_05b_021503
REFCLK_P
IBUFGDS
BUFGMUX
REFCLK_N
REFCLK2_P
REFCLK2_N
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English