RocketIO™ Transceiver User Guide www.xilinx.com 121
UG024 (v3.0) February 22, 2007
R
Chapter 4
Simulation and Implementation
Simulation Models
SmartModels
SmartModels are encrypted versions of the actual HDL code. These models allow the user
to simulate the actual functionality of the design without having access to the code itself.
A simulator with SmartModel capability is required to use SmartModels.
The models must be extracted before they can be used. For information on how to extract
the SmartModels under ISE 5.1i, see Solution Record 15501
.
HSPICE
HSPICE is an analog design model that allows simulation of the RX and TX high-speed
transceiver. To obtain these HSPICE models, go to the Xilinx Download Center at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
.
Select HSPICE and Eldo Models and then Virtex-II Pro from the pull-down menus.
Online registration is required. Follow the instructions on the web page to register.
Implementation Tools
Par
For place and route, the transceiver has one restriction. This is required when channel
bonding is implemented. Because of the delay limitations on the CHBONDO to CHBONDI
ports, linking of the Master to a Slave_1_hop must run either in the X or Y direction, but not
both.
In Figure 4-1, the two Slave_1_hops are linked to the master in only one direction. To
navigate to the other slave (a Slave_2_hops), both X and Y displacement is needed. This
slave needs one level of daisy-chaining, which is the basis of the Slave_2_hops setting.
Figure 4-2 shows the channel bonding mode and linking for a 2VP50, which (optionally)
contains more transceivers (16) per chip.
Product Not Recommended for New Designs
To Next Page
Loading...
Need help?
General
