Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 123
UG024 (v3.0) February 22, 2007
MGT Package Pins
R
MGT Package Pins
The MGT is a hard core placed in the FPGA fabric; all package pins for the MGTs are
dedicated on the Virtex-II Pro device. This is shown in the package pin diagrams in the
Virtex-II Pro Platform FPGA User Guide
. When creating a design, LOC constraints must be
used to implement a specific MGT on the die. This LOC constraint also determines which
package pins are used. Table 4-1 shows the correlation between the LOC grid and the
package pins themselves. The pin numbers are TXNPAD, TXPPAD, RXPPAD, and
RXNPAD, respectively. The power pins are adjacent to these pins in the package pin
diagrams of the User Guide.
Table 4-1: LOC Grid & Package Pins Correlation for FG256/456 & FF672
LOC
Constraints
FG256 FG456 FF672
2VP2/2VP4 2VP2/2VP4 2VP7 2VP2/2VP4 2VP7
GT_X0_Y0 T4, T5, T6, T7 AB7, AB8,
AB9, AB10
AB3, AB4,
AB5, AB6
AF18, AF17,
AF16, AF15
AF23, AF22,
AF21, AF20
GT_X0_Y1 A4, A5, A6,
A7
A7, A8, A9,
A10
A3, A4, A5,
A6
A18, A17,
A16, A15
A23, A22,
A21, A20
GT_X1_Y0 T10, T11, T12,
T13
AB13,AB14,
AB15, AB16
AB7, AB8,
AB9, AB10
AF12, AF11,
AF10, AF9
AF18, AF17,
AF16, AF15
GT_X1_Y1 A10, A11,
A12, A13
A13, A14,
A15, A16
A7, A8, A9,
A10
A12, A11,
A10, A9
A18, A17,
A16, A15
GT_X2_Y0 AB13, AB14,
AB15, AB16
AF12, AF11,
AF10, AF9
GT_X2_Y1 A13, A14,
A15, A16
A12, A11,
A10, A9
GT_X3_Y0 AB17, AB18,
AB19, AB20
AF7, AF6,
AF5, AF4
GT_X3_Y1 A17, A18,
A19, A20
A7, A6, A5,
A4
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English