Xilinx RocketIO User Manual

38 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 1: RocketIO Transceiver Overview
R
Byte Mapping
Most of the 4-bit wide status and control buses correlate to a specific byte of TXDATA or
RXDATA. This scheme is shown in Table 1-9. This creates a way to tie all the signals
together regardless of the data path width needed for the GT_CUSTOM. All other
primitives with specific data width paths and all byte-mapped ports are affected by this
situation. For example, a 1-byte wide data path has only 1-bit control and status bits
(TXKERR[0]) correlating to the data bits TXDATA[7:0]. Footnote 3 in Table 1-5 shows the
ports that use byte mapping.
RX_DECODE_USE TRUE TRUE TRUE
RX_LOS_INVALID_INCR 1
(1)
1
(1)
1
(1)
RX_LOS_THRESHOLD 4
(1)
4
(1)
4
(1)
RX_LOSS_OF_SYNC_FSM TRUE
(1)
TRUE
(1)
TRUE
(1)
SERDES_10B FALSE
(1)
FALSE
(1)
FALSE
(1)
TERMINATION_IMP 50
(1)
50
(1)
50
(1)
TX_BUFFER_USE TRUE TRUE TRUE
TX_CRC_FORCE_VALUE 11010110
(1)
11010110
(1)
11010110
(1)
TX_CRC_USE FALSE
(1)
FALSE
(1)
FALSE
(1)
TX_DATA_WIDTH N
(2)
N
(2)
N
(2)
TX_DIFF_CTRL 500
(1)
500
(1)
500
(1)
TX_PREEMPHASIS 0
(1)
0
(1)
0
(1)
Notes:
1. Modifiable attribute for specific primitives.
2. Depends on primitive used: either 1, 2, or 4.
3. CRC_EOP and CRC_SOP are not applicable for this primitive.
Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND,
and GT_XAUI (Continued)
Attribute
Default
GT_FIBRE_CHAN
Default
GT_INFINIBAND
Default
GT_XAUI
Table 1-9: Control/Status Bus Association to Data Bus Byte Paths
Control/Status Bit Data Bits
[0] [7:0]
[1] [15:8]
[2] [23:16]
[3] [31:24]
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Form Factor	Integrated into Xilinx FPGAs and SoCs
Technology	CMOS
Category	Transceiver
Protocol Support	Aurora, Ethernet, CPRI
Package	Integrated into FPGA/SoC package
Data Rate	Up to 28.05 Gbps
Signal Integrity	Integrated equalization, pre-emphasis, and decision feedback equalization (DFE)

Summary

Chapter 1: RocketIO Transceiver Overview

Basic Architecture and Capabilities

List of Available Ports

Chapter 2: Digital Design Considerations

Clocking

BREFCLK

Digital Clock Manager (DCM) Examples

Half-Rate Clocking Scheme

RXRECCLK

Data Path Latency

Reset/Power Down

8B/10B Encoding/Decoding

SERDES Alignment

Explains SERDES alignment for serial data transmission and reception.

ENPCOMMAALIGN, ENMCOMMAALIGN

Clock Recovery

Introduces clock/data recovery circuits for synchronous serial data reception.

Clock Correction

Synchronization Logic

Explains the importance of knowing data validity and MGT synchronization.

Channel Bonding (Channel Alignment)

Explains channel bonding for aligning multiple transceivers for higher data rates.

CRC (Cyclic Redundancy Check)

Explains CRC as a procedure to detect errors in received data.

Fabric Interface (Buffers)

Explains the reasons for including buffers in transmit and receive paths.

Chapter 3: Analog Design Considerations

Serial I/O Description

Pre-emphasis Techniques

Explains techniques to boost voltage swing for signal integrity over lossy media.

Differential Receiver

Describes the differential receiver's input and parameters.

Jitter

Clock and Data Recovery

Explains the CDR function for locking to input data streams and deriving clocks.

PCB Design Requirements

Outlines requirements for reliable RocketIO transceiver operation.

Power Conditioning

Details requirements for power filtering and noise isolation for transceiver pins.

Voltage Regulator Selection and Use

Provides criteria for selecting linear regulators for RocketIO transceiver supplies.

Passive Filtering

Explains the need for passive filter networks on power supply pins for noise isolation.

High-Speed Serial Trace Design

Provides guidelines for routing high-speed serial traces on PCBs.

Differential Trace Design

Details trace geometry and spacing for achieving required differential impedance.

AC and DC Coupling

Explains when to use AC or DC coupling for transceiver signal paths.

Reference Clock

Specifies requirements for accurate reference clocks for transceiver operation.

Other Important Design Notes

Powering the RocketIO Transceivers

Emphasizes connecting all transceivers to power and ground, even unused ones.

The POWERDOWN Port

Chapter 4: Simulation and Implementation

Simulation Models

MGT Package Pins

Details package pin assignments for MGTs and their correlation to LOC constraints.

Appendix A: RocketIO Transceiver Timing Model

Timing Parameters

Explains the designations of timing parameters used in tables.

Setup/Hold Times of Inputs Relative to Clock

Clock to Output Delays

Clock Pulse Width

Appendix B: 8B/10B Valid Characters

Valid Data Characters

Valid Control Characters (K-Characters)

Appendix C: Related Online Documents

Application Notes

Virtex-II Pro RocketIO Multi-Gigabit Transceiver Characterization Summary