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Xilinx RocketIO User Manual

Xilinx RocketIO
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RocketIO™ Transceiver User Guide www.xilinx.com 15
UG024 (v3.0) February 22, 2007
Chapter 1: RocketIO Transceiver Overview
Table 1-1: Number of RocketIO Cores per Device Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 1-2: Communications Standards Supported by RocketIO Transceiver . . . . . . . . . 21
Table 1-3: Serial Baud Rates and the SERDES_10B Attribute . . . . . . . . . . . . . . . . . . . . . . . 22
Table 1-4: Supported RocketIO Transceiver Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 1-5: GT_CUSTOM
(1)
, GT_AURORA, GT_FIBRE_CHAN
(2)
, GT_ETHERNET
(2)
,
GT_INFINIBAND, and GT_XAUI Primitive Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 1-6: RocketIO Transceiver Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 1-7: Default Attribute Values: GT_AURORA, GT_CUSTOM, GT_ETHERNET. 34
Table 1-8: Default Attribute Values: GT_FIBRE_CHAN, GT_INFINIBAND,
and GT_XAUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 1-9: Control/Status Bus Association to Data Bus Byte Paths. . . . . . . . . . . . . . . . . . . 38
Chapter 2: Digital Design Considerations
Table 2-1: Clock Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-2: Reference Clock Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 2-3: BREFCLK Pin Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 2-4: Data Width Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 2-5: DCM Outputs for Different DATA_WIDTHs . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 2-6: Latency through Various Transmitter Components/Processes. . . . . . . . . . . . . 57
Table 2-7: Latency through Various Receiver Components/Processes. . . . . . . . . . . . . . . . 57
Table 2-8: Reset and Power Control Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 2-9: Power Control Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 2-10: 8B/10B Bypassed Signal Significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 2-11: Running Disparity Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 2-12: Possible Locations of Comma Character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 2-13: Effects of Comma-Related Ports and Attributes . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 2-14: Data Bytes Allowed Between Clock Corrections as a Function of
REFCLK Stability and IDLE Sequences Removed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 2-15: Clock Correction Sequence / Data Correlation for 16-Bit Data Port . . . . . . . 74
Table 2-16: Applicable Clock Correction Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 2-17: RXCLKCORCNT Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 2-18: Bonded Channel Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 2-19: Master/Slave Channel Bonding Attribute Settings. . . . . . . . . . . . . . . . . . . . . . 81
Table 2-20: Effects of CRC on Transceiver Latency
(1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 2-21: Global and Local Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 2-22: Serial Speed Ranges as a Function of SERDES_10B. . . . . . . . . . . . . . . . . . . . . 91
Table 2-23: LOOPBACK Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 2-24: 32-bit RXDATA, Aligned versus Misaligned. . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Schedule of Tables
Product Not Recommended for New Designs

Table of Contents

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Xilinx RocketIO Specifications

General IconGeneral
BrandXilinx
ModelRocketIO
CategoryTransceiver
LanguageEnglish

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