14 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
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Figure 3-3: K28.5+ with Pre-Emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 3-4: Eye Diagram, 10% Pre-Emphasis, 20" FR4, Worst-Case Conditions . . . . . . 106
Figure 3-5: Eye Diagram, 33% Pre-Emphasis, 20" FR4, Worst-Case Conditions . . . . . . 106
Figure 3-6: MGT Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Figure 3-7: Power Supply Circuit Using Approved Regulator . . . . . . . . . . . . . . . . . . . . . 110
Figure 3-8: Power Filtering Network on Devices with Internal & External Capacitors 111
Figure 3-9: Example Power Filtering PCB Layout for Four MGTs, in Device with
Internal Capacitors, Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figure 3-10: Example Power Filtering PCB Layout for Four MGTs, In Device with
External Capacitors, Top Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Figure 3-11: Example Power Filtering PCB Layout for Four MGTs, in Device with
External Capacitors, Bottom Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 3-12: Single-Ended Trace Geometry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 3-13: Microstrip Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-14: Stripline Edge-Coupled Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-15: AC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 3-16: DC-Coupled Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Figure 3-17: LVPECL Reference Clock Oscillator Interface. . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 3-18: LVPECL Reference Clock Oscillator Interface (On-Chip Termination) . . 119
Figure 3-19: LVDS Reference Clock Oscillator Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 3-20: LVDS Reference Clock Oscillator Interface (On-Chip Termination) . . . . 119
Chapter 4: Simulation and Implementation
Figure 4-1: XC2VP2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 4-2: XC2VP50 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Appendix A: RocketIO Transceiver Timing Model
Figure A-1: RocketIO Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Figure A-2: RocketIO Transceiver Timing Relative to Clock Edge . . . . . . . . . . . . . . . . . 133
Appendix B: 8B/10B Valid Characters
Appendix C: Related Online Documents
Product Not Recommended for New Designs
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