Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 153
UG024 (v3.0) February 22, 2007
Numerics
8B/10B Encoding/Decoding
bypassing
66
decoder 60
encoder 60
overview 60
ports and attributes 61
serial output format 66
8B/10B Valid Characters 135
A
AC and DC Coupling 117
Attributes & Ports (by function)
8B/10B encoding/decoding
61
buffers, fabric interface 90
channel bonding 81
clock correction 73
CRC 85
SERDES alignment 67
synchronization logic 76
Attributes (defined)
ALIGN_COMMA_MSB
67
CHAN_BOND__SEQ_LEN 81
CHAN_BOND_LIMIT 82
CHAN_BOND_MODE 81
CHAN_BOND_OFFSET 82
CHAN_BOND_ONE_SHOT 81
CHAN_BOND_SEQ_*_* 81
CHAN_BOND_SEQ_2_USE 81
CHAN_BOND_WAIT 82
CLK_COR_INSERT_IDLE_FLAG
75
CLK_COR_KEEP_IDLE 75
CLK_COR_REPEAT_WAIT 75
CLK_COR_SEQ_*_* 74
CLK_COR_SEQ_LEN 75
CLK_CORRECT_USE 73
COMMA_10B_MASK 70
CRC_END_OF_PACKET 88
CRC_FORMAT 85
CRC_START_OF_PACKET 88
DEC_MCOMMA_DETECT 70
DEC_PCOMMA_DETECT 70
DEC_VALID_COMMA_ONLY 70
MCOMMA_10B_VALUE 70
MCOMMA_DETECT 70
PCOMMA_10B_VALUE 70
PCOMMA_DETECT 70
PRE_EMPHASIS 91
RX_BUFFER_USE 74, 90
RX_CRC_USE 85
RX_DATA_WIDTH 90
RX_DECODE_USE 61
RX_LOS_INVALID_INCR 77
RX_LOS_THRESHOLD 77
RX_LOSS_OF_SYNC_FSM 77
SERDES_10B 90
TERMINATION_IMP 91
TX_BUFFER_USE 90
TX_CRC_FORCE_VALUE 89
TX_CRC_USE 85
TX_DATA_WIDTH 90
TX_DIFF_CTRL 91
Attributes (table) 29
B
BREFCLK
and REF_CLK_V_SEL
32, 41
and REFCLKSEL 25, 41
and serial speed 39
pin numbers 41
when & how to use 41
Buffers, Fabric Interface 89
ports and attributes 90
transmitter and elastic (receiver) 89
Byte Mapping 38
C
Channel Bonding (Alignment) 79
operation 80
ports and attributes 81
troubleshooting 83
Vitesse channel bonding sequence
receive
65
transmit 64
Characters, valid (tables) 135
Clock Correction (Recovery)
clock recovery
72
overview 71
ports and attributes 73
Clock/Data Recovery (CDR) parameters
108
Clocking 39
clock and data recovery 72
clock correction (recovery) 71
clock dependency 56
clock descriptions 127
clock pulse width 130
clock ratio 42
clock recovery 72
clock signals 39
clock synthesizer 71
clock-to-output delays 129
code examples
1-byte clock
50
2-byte clock 43
4-byte clock 46
half-rate clocking scheme 54
multiplexed clocking scheme
with DCM
55
without DCM 55
Control Characters, valid (table) 143
Coupling, AC and DC 117
CRC (Cyclic Redundancy Check) 84
generation 84
latency 85
operation 84
ports and attributes 85
support limitations 89
D
Data Characters, valid (table) 135
Data Path Latency 57
Deserializer 67
Deterministic Jitter (DJ) 108
Differential Receiver 107
Differential Trace Design 116
H
Half-Rate Clocking Scheme 54
HDL Code Examples
Verilog
1-byte clock
52
2-byte clock 45
32-bit alignment design 95
4-byte clock 49
VHDL
1-byte clock
50
Index
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English