Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 75
UG024 (v3.0) February 22, 2007
Clock Recovery
R
CLK_COR_SEQ_LEN
To define the CCS length, this attribute takes the integer value 1, 2, 3, or 4. Table 2-16 shows
which sequences are used for the four possible settings of CLK_COR_SEQ_LEN.
CLK_COR_INSERT_IDLE_FLAG,
CLK_COR_KEEP_IDLE,
CLK_COR_REPEAT_WAIT
These attributes help control how clock correction is implemented.
CLK_COR_INSERT_IDLE_FLAG is a TRUE/FALSE attribute that defines the output of
the RXRUNDISP port. When set to TRUE, RXRUNDISP is raised for the first byte of each
inserted (repeated) clock correction sequence (8B/10B decoding enabled). When set to
FALSE (default), RXRUNDISP denotes the running disparity of RXDATA (8B/10B
decoding enabled).
CLK_COR_KEEP_IDLE is a TRUE/FALSE attribute that controls whether or not the final
byte stream must retain at least one clock correction sequence. When set to FALSE
(default), the clock correction logic is allowed to remove all clock correction sequences if
needed to recenter the elastic buffer. When set to TRUE, it forces the clock correction logic
to retain at least one clock correction sequence per continuous stream of clock correction
sequences.
Example: Elastic buffer is 75% full and clock correction is needed. (IDLE is the defined clock
correction sequence.)
Data stream written into elastic buffer:
Data stream read out of elastic buffer (CLK_COR_KEEP_IDLE = FALSE)
Data stream read out of elastic buffer (CLK_COR_KEEP_IDLE = TRUE)
CLK_COR_REPEAT_WAIT is an integer attribute (0-31) that controls frequency of
repetition of clock correction operations. This attribute specifies the minimum number of
RXUSRCLK cycles without clock correction that must occur between successive clock
corrections. For example, if this attribute is 3, then at least three RXUSRCLK cycles without
Table 2-16: Applicable Clock Correction Sequences
CLK_COR_SEQ_LEN
CLK_COR_SEQ_1
That Are Applicable
CLK_COR_SEQ_2
That Are Applicable
(1)
1 1_1 2_1
2 1_1, 1_2 2_1, 2_2
3 1_1, 1_2, 1_3 2_1, 2_2, 2_3
4 1_1, 1_2, 1_3. 1_4 2_1, 2_2, 2_3, 2_4
Notes:
1. Applicable only if CLK_COR_SEQ_2_USE is set to TRUE.
D0 IDLE IDLE IDLE IDLE D1 D2
D0 D1 D2
D0
IDLE D1 D2
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English