Xilinx RocketIO User Manual

94 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 2: Digital Design Considerations
R
When RXDATA is 32-bit aligned, the logic should pass RXDATA though to the protocol
logic without modification. A properly aligned data flow is shown in Figure 2-29.
When RXDATA is 32-bit misaligned, the word requiring alignment is split between
consecutive RXDATA words in the data stream, as shown in Figure 2-30. (RXDATA_REG
in the figure refers to the design example code in “32-bit Alignment Design,” page 95.)
This conditional shift/delay operation on RXDATA also must be performed on the status
outputs RXNOTINTABLE, RXDISPERR, RXCHARISK, RXCHARISCOMMA, and
RXRUNDISP in order to keep them properly synchronized with RXDATA.
It is not possible to adjust RXCLKCORCNT appropriately for shifted/delayed RXDATA,
because RXCLKCORCNT is summary data, and the summary for the shifted case cannot
be recalculated.
Table 2-24: 32-bit RXDATA, Aligned versus Misaligned
RXDATA
[31:24]
RXDATA
[23:16]
RXDATA
[15:8]
RXDATA
[7:0]
32-bit aligned BC 95 B5 B5
CHARISCOMMA 1000
32-bit misaligned pp pp BC 95
CHARISCOMMA 0010
Figure 2-29: RXDATA Aligned Correctly
Figure 2-30: Realignment of RXDATA
BC95B5B5
TXDATA
RXDATA
ALIGNED_DATA
BC95B5B5
BC95B5B5
FDB53737
FDB53737
FDB53737
45674893
45674893
45674893
nnnnnnnn nnnnnnnn
nnnnnnnnnnnnnnnn
pppppppp
nnnnnnnn
ug024_33_091602
BC95B5B5
TXDATA
RXDATA
ALIGNED_DATA
pppp BC95
BC95B5B5
FDB53737
B5B5FDB5
FDB53737
45674893
37374567
45674893
nnnnnnnn nnnnnnnn
nnnnnnnn
4893 nnnn
RXDATA_REG[15:0]
BC95
pppp FDB5 4567 nnnn
pppppppp pppppppp
ug024_34_091602
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English