Xilinx Virtex UltraScale+ FPGAs User Manual

In all modes, codewords are 5440 bits in length. The nal 300 bits of output data (bits 5140 to
5439) is the FEC parity as received and possibly corrected by the RS decoder. In most
applicaons, the parity bits can be discarded.
50G Ethernet
Up to two channels of 50G Ethernet with KP4 FEC can be implemented as per IEEE Dra
Standard for Ethernet Amendment: Media Access Control Parameters for 50 Gb/s and Physical Layers
and Management Parameters for 50 Gb/s, 100 Gb/s, and 200 Gb/s Operaon (IEEE Std 802.3cd
Clause 134). Transcoding should be enabled in the GTM Wizard IP for this mode. The nominal
pre-FEC PCS data rate is 51.5625 Gb/s, and the nominal post-FEC line rate is 53.125 Gb/s.
100G Ethernet
One channel of 100G Ethernet with KP4 FEC can be implemented as per IEEE Std 802.3-2015
Clause 91. Transcoding should be enabled in the GTM Wizard IP for this mode. The nominal
aggregate pre-FEC PCS data rate is 103.125 Gb/s and the nominal aggregate post-FEC line rate
is 106.25 Gb/s.
100G OTN FlexO
One channel of 100G OTN FlexO with a KP4 FEC can be implemented as per ITU-T G.709.1,
Flexible OTN Short-Reach Interface. Transcoding should be disabled in the GTM Wizard IP for this
mode. The nominal aggregate post-FEC line rate is 111.81 Gb/s.
100G Interlaken
One channel of 100G Interlaken with KP4 FEC can be implemented as per the Interlaken Reed-
Solomon Forward Error Correcon Extension Protocol Denion. Transcoding should be disabled in
the GTM Wizard IP for this mode. Line rates up to 58 Gb/s are possible.
Proprietary Backplane Protocols with FEC up to 58 Gb/s
When FEC is enabled in 50G raw mode (with or without scrambling), driving
FECCTRLRXnBITSLIPFS High causes the FEC decoder in slice n to move the starng posion of
the decoded codeword to the next bit posion. By repeatedly slipping the serial data in this way
unl FEC decoding is successful, alignment to the incoming codeword stream can be achieved
without the need for alignment markers to be inserted in the data.
When the FEC is enabled in any mode other than the 50G raw modes, these signals are ignored.
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 112
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English