Xilinx Virtex UltraScale+ FPGAs User Manual

RX Interface
The RX interface is the gateway to the RX datapath of the GTM transceiver. Applicaons receive
data through the GTM transceiver by reading data to the RXDATA port on the posive edge of
RXUSRCLK2. Port widths can be 64 and 128 bits for NRZ mode, or 80, 128, 160, and 256 bits
for PAM4 mode. The rate of the parallel clock (RXUSRCLK2) at the interface is determined by the
RX line rate and the width of the RXDATA port. A second parallel clock (RXUSRCLK) must be
provided for the internal PCS logic in the receiver. This secon shows how to drive the parallel
clocks and explains the constraints on those clocks for correct operaon.
Interface Width Configuration
The GTM transceiver contains a 64-bit internal datapath in NRZ mode, and an 80-bit and 128-bit
internal datapath in PAM4 mode that is congurable by seng the TX_INT_DATA_WIDTH
aribute. When the FEC is enabled, only the 80-bit internal datapath can be used. The interface
width is congurable by seng the TX_DATA_WIDTH aribute. In NRZ mode,
TX_DATA_WIDTH can be congured to 64 or 128 bits. In PAM4 mode, TX_DATA_WIDTH can
be congured to 80, 128, 160, or 256 bits. When the FEC is enabled, only the 80-bit or 160-bit
RX internal data width can be selected.
The following table shows how the interface width for RX datapath is selected.
Table 69: RX Interface Datapath Configuration
Encod
ing
FEC
Allowed?
RX_DATA_WIDTH
Encoding
RX Data Width
Selection
RX_INT_DATA_WID
TH Encoding
RX Internal
Datapath
Selection
NRZ No 0 64 0 64
No 2 128 0 64
PAM4 Yes 1 80 1 80
Yes 3 160 1 80
No 2 128 2 128
No 4 256 2 128
The following gure shows the RX data received.
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 113
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English