Xilinx Virtex UltraScale+ FPGAs User Manual

Enable RX Pattern Checker for 80-bit or 160-bit Data Widths
1. Using the DRP interface, write the following values to CH[0/1]_RX_PCS_CFG0[4:0] (address
0x080 for CH0, 0x280 for CH1):
a. CH[0/1]_RX_PCS_CFG0[4:0] = 0x12 for 80-bit data width mode.
b. CH[0/1]_RX_PCS_CFG0[4:0] = 0x14 for 160-bit data width mode.
2. Enable the PRBS checker by seng CH[0/1]_RXPRBSPTN to the required value for the
desired paern.
RX PRBS paern checker is enabled.
Disable RX Pattern Checker for 80-bit or 160-bit Data Widths
1. Disable the PRBS checker by seng CH[0/1]_RXPRBSPTN[3:0] to 4’b0000.
2. Using the DRP interface, write the following values to CH[0/1]_RX_PCS_CFG0[4:0] (address
0x083 for CH0, 0x283 for CH1):
a. CH[0/1]_RX_PCS_CFG0[4:0] = 0x09 for 80-bit data width mode.
b. CH[0/1]_RX_PCS_CFG0[4:0] = 0x0B for 160-bit data width mode.
3. Set CH[0/1]_RXPMARESETMASK = 0x0.
4. Toggle CH[0/1]_GTRXRESET High and Low.
5. Wait for CH[0/1]_RXRESETDONE to toggle High.
6. Set CH[0/1]_RXPMARESETMASK = 0x7F.
RX PRBS paern checker is disabled.
RX Buffer
The GTM transceiver RX datapath has two internal parallel clock domains used in the PCS: the
interface with PMA parallel clock domain (XCLK), and the PCS internal clock domain
(RXUSRCLK). To receive data, the RX buer provides data width conversion between these clock
domains when necessary, depending on the operang data width and encoding mode. The
following gure shows the RX datapath clock domains.
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English

Summary

Chapter 1: Transceiver and Tool Overview

Features

Key features of the GTM transceiver, including supported line rates and modulation.

UltraScale+ FPGAs GTM Transceivers Wizard

Description of the wizard tool for configuring GTM transceivers.

Chapter 2: Shared Features

Reference Clock Input/Output Structure

Reference Clock Selection and Distribution

Explanation of reference clock input options and selection architecture.

LCPLL

Reset and Initialization

Steps for initializing the GTM transceiver TX and RX datapaths.

Dynamic Reconfiguration Port

Chapter 3: Transmitter

TX Interface

Gateway to the TX datapath, including data width and clocking.

TX FEC

Details on the Integrated KP4 Reed-Solomon Forward Error Correction.

TX Pattern Generator

Generates industry-standard PRBS patterns for signal integrity testing.

TX Configurable Driver

Controls output buffer characteristics like voltage and pre-emphasis.

Chapter 4: Receiver

RX Equalizer

Compensates for channel attenuation and distortion using CTLE, FFE, and DFE.

RX CDR

Clock Data Recovery circuit for extracting clock and data from incoming streams.

RX Margin Analysis

RX Pattern Checker

RX FEC

Details on the Integrated KP4 Reed-Solomon Forward Error Correction.

RX Interface

Gateway to the RX datapath, including data width and clocking.

Chapter 5: Board Design Guidelines

Pin Description and Design Guidelines

Reference Clock