Xilinx Virtex UltraScale+ FPGAs User Manual

• Meet or exceed the reference clock characteriscs as specied in the UltraScale+ device data
sheets.
• Meet or exceed the reference clock characteriscs as specied in the standard for which the
GTM transceiver provides physical layer support.
• Fulll the oscillator vendor’s requirement regarding power supply, board layout, and noise
specicaon.
• Provide a dedicated point-to-point connecon between the oscillator and GTM transceiver
Dual clock input pins.
• Keep impedance disconnuies on the dierenal transmission lines to a minimum
(impedance disconnuies generate jier).
Reference Clock Interface
LVDS
The following gure shows how an LVDS oscillator is connected to a reference clock input of a
GTM transceiver.
Figure 53: Interfacing an LVDS Oscillator to the GTM Transceiver Reference Clock
Input
LVDS Oscillator
0.01 µF
0.01 µF
GTM Transceiver
Reference Clock
Input Buffer
Internal to
UltraScale+ Device
X20934-053118
LVPECL
The following gure shows how an LVPECL oscillator is connected to a reference clock input of a
GTM transceiver.
Chapter 5: Board Design Guidelines
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 123
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English