Xilinx Virtex UltraScale+ FPGAs User Manual

Appendix A
DRP Address Map of the GTM
Transceiver in UltraScale+ FGPAs
GTM_DUAL Primitive DRP Address Map
The following table lists the DRP map of the GTM_DUAL primive sorted by address.
Note: DO NOT modify the reserved bits. Aributes are not described explicitly and are set automacally
by the UltraScale FGPAs Transceiver Wizard. These aributes must be le at their defaults, except for use
cases that explicitly request dierent values.
Table 75: DRP Map of GTM_DUAL Primitive
DRP
Addres
s
DRP
Bits
R/W Attribute Name Attribute Bits
Attribute
Encoding
DRP
Encoding
0x001 [15:0] R/W CH0_TX_DRV_CFG0 [15:0] 0–65535 0–65535
0x002 [15:0] R/W CH0_TX_DRV_CFG1 [15:0] 0–65535 0–65535
0x003 [15:0] R/W CH0_TX_DRV_CFG2 [15:0] 0–65535 0–65535
0x004 [15:0] R/W CH0_TX_ANA_CFG1 [15:0] 0–65535 0–65535
0x005 [15:0] R/W CH0_TX_ANA_CFG2 [15:0] 0–65535 0–65535
0x006 [15:0] R/W CH0_TX_ANA_CFG3 [15:0] 0–65535 0–65535
0x007 [15:0] R/W CH0_TX_DRV_CFG3 [15:0] 0–65535 0–65535
0x008 [15:0] R/W CH0_TX_DRV_CFG4 [15:0] 0–65535 0–65535
0x009 [15:0] R/W CH0_TX_DRV_CFG5 [15:0] 0–65535 0–65535
0x00a [15:0] R/W CH0_TX_LPBK_CFG0 [15:0] 0–65535 0–65535
0x00b [15:0] R/W CH0_TX_LPBK_CFG1 [15:0] 0–65535 0–65535
0x00c [15:0] R/W CH0_TX_ANA_CFG4 [15:0] 0–65535 0–65535
0x00d [15:0] R/W CH0_TX_CAL_CFG0 [15:0] 0–65535 0–65535
0x00e [15:0] R/W CH0_TX_CAL_CFG1 [15:0] 0–65535 0–65535
0x00f [15:0] R/W CH0_TX_ANA_CFG0 [15:0] 0–65535 0–65535
0x010 [15:0] R/W CH0_RX_ANA_CFG0 [15:0] 0–65535 0–65535
0x011 [15:0] R/W CH0_RX_ANA_CFG1 [15:0] 0–65535 0–65535
0x012 [15:0] R/W CH0_RX_PAD_CFG0 [15:0] 0–65535 0–65535
0x013 [15:0] R/W CH0_RX_PAD_CFG1 [15:0] 0–65535 0–65535
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 133
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English