Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 33: Transmitted PAM4 Signal Bit Encoding
Ports and Attributes
The following table denes the aributes required for TX Gray encoder control.
Table 41: Gray Encoder Attributes
Attribute Type Description
CH[0/1]_TX_PCS_CFG0 16-bit Reserved.
Bit Name Address Description
TX_GRAY_ENDIAN [13] In PAM4 mode, this attribute controls transmitted
endianness. In NRZ mode, the default Wizard value must be
used.
1’b0: Non-inverting.
1’b1: Inverting.
TX_GRAY_BYP_EN
[12] In PAM4 mode, this attribute enables Gray encoding. In NRZ
mode, the default Wizard value must be used.
1’b0: Enables Gray encoding.
1’b1: Disables Gray encoding.
IMPORTANT! In PAM4 mode, if Gray encoder is enabled for the transmier, the receiver Gray decoder
should also be enabled for proper data recovery.
TX Pre-Coder
GTM transmiers in UltraScale+ devices support pre-coding. Pre-coding can be used to reduce
receiver decision feedback equalizaon (DFE) error propagaon by reducing 1-tap burst error
runs into two errors for every error event.
Chapter 3: Transmitter
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 72
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English