Xilinx Virtex UltraScale+ FPGAs User Manual

Use Mode External AC Coupling
Term
Voltage
(mV)
Suggested Protocols and Usage Notes
1 On 800 Attribute settings:
PAD_RTERM_VCOM_MODE = 2’b11
PAD_RTERM_VCOM_LVL = 4’b1010
Figure 38: Use Mode 1
+
–
UltraScale+ DeviceBoard
ACJTAG RX
ACJTAG RX
50Ω
50Ω
Programmable
MGTAVTT
MGTAVTT
~100 nF
~100 nF
PAD_RTERM_VCOM_MODE = 2'b11
PAD_RTERM_VCOM_LVL = 4'b1010
X20923-110518
RX Equalizer
A serial link bit error rate (BER) performance is a funcon of the transmier, transmission media,
and receiver. The transmission media of the channel is bandwidth-limited, and the signal traveling
through is subjected to aenuaon and distoron.
The GTM receiver is an ADC-based buer that breaks the equalizer into two domains: analog
and digital. The incoming signal rst passes through the analog stage consisng of a CTLE and
AGC stage. The signal is then digized by the ADC, and passes through the Feed-Forward
Equalizer (FFE) and Decision-Feedback-Equalizer (DFE), as shown in the following gure.
Chapter 4: Receiver
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 87
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English