Xilinx Virtex UltraScale+ FPGAs User Manual

Printed Circuit Board
Because the impedance between the power planes and GND has been kept low on the die and in
the package, the board design has a much more relaxed requirement for decoupling on the
printed circuit board. The primary purpose of the PCB decoupling capacitors is to provide noise
isolaon between the transceiver power supply pins and the external noise sources. Some
examples of external noise sources are:
• Power supply regulator circuits
• On-board digital switching circuits
• SelectIO signals from the UltraScale+ device
Decoupling capacitors should be provided on the PCB near the GTM transceiver power pins.
These capacitors reduce the impedance of the PCB power distribuon network. The reduced
impedance of the PDN provides a means to aenuate noise from external sources before it can
get into the device package power planes. The noise at the power pins should be less than
10 mVpp over the band from 10 kHz to 200 MHz.
PCB Design Checklist
The following table is a checklist of items that can be used to design and review any GTM
transceiver PCB schemac and layout.
Table 74: GTM Transceiver PCB Design Checklist
Pins Recommendations
MGTREFCLKP
MGTREFCLKN
When configured as an input:
• Use AC coupling capacitors for connection to oscillator.
• For AC coupling capacitors, see Reference Clock Interface.
• Reference clock oscillator output must comply with the minimum and maximum input
amplitude requirements for these input pins. See the UltraScale+ device data sheets (see
http://www.xilinx.com/documentation).
When configured as an output:
• Use AC coupling capacitors for connection to receiving device.
• For AC coupling capacitors use 0.01 μF.
• For output signal characteristics, see the Virtex UltraScale device data sheet (see http://
www.xilinx.com/documentation).
• If reference pins are not used, leave the associated pin pair unconnected. However, if the
IBUFDS_GTME3/4 is instantiated in the design but not used, the associated pin pair should be
connected to GND.
Chapter 5: Board Design Guidelines
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 129
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English