Xilinx Virtex UltraScale+ FPGAs User Manual

Power Down
The GTM transceiver oers dierent levels of power control. Each channel in each direcon can
be powered down separately. The PLLPD port directly aects the LCPLL.
Ports and Attributes
The following table denes the power-down ports.
Table 20: Power-Down Ports
Port Dir Clock Domain Description
PLLPD In Async This active-Low signal powers down the LCPLL.
The following table denes the power-down aributes.
Table 21: Power-Down Attributes
Attribute Type Description
CH[0/1]_TX_ANA_CFG0 16-bit Reserved.
Bit Name Address Description
TXPWRDN_B [1:0] Powers down channel TX:
2’b00: Power down.
2’b11: Power up.
RST_CFG 16-bit Reserved.
Bit Name Address Description
RX_PDB_CH0 [2] This active-Low signal powers down channel 0 RX.
RX_PDB_CH1 [3] This active-Low signal powers down channel 1 RX.
PLL Power Down
To acvate the LCPLL power-down mode, the acve-Low PLLPD signal is asserted. When PLLPD
is deasserted, the LCPLL is powered down. As a result, all clocks derived from the PLL are
stopped. Recovery from this power state is indicated by the PLL lock signal PLLLOCK.
TX and RX Power Down
TX and RX power control signals can be used independently. Only two power states are
supported, as shown in the following table. Powering up/down mulple lanes in a Dual or
mulple Duals aects the power supply regulaon circuit (see Power Up/Down and Reset on
Mulple Lanes).
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 45
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English