Xilinx Virtex UltraScale+ FPGAs User Manual

• Power distribuon network
• Coupling from other circuits
Each of these noise sources must be considered in the design and implementaon of the GTM
transceiver analog power supplies. The total peak-to-peak noise as measured at the input pin of
the UltraScale device should not exceed 10 mVpk-pk.
Power Up/Down and Reset on Multiple Lanes
The operang state of the GTM transceiver can be controlled through the enabling and disabling
of the power down and reset controls (see Reset and Inializaon and Power Down). When the
GTM transceiver’s operang state is changed by either changing the power down state or the
reset state, the load current as seen by the on-board power distribuon network (PDN) and the
power supply regulator is also changed. When the load current changes, the power supply
regulator must sense the change in the load current and compensate for this change to maintain
the design supply voltage. The eect of a delay in the change in the load current can result in a
temporary spike or dip in the power supply voltage. When the operang state of the GTM
transceiver goes from power down to power up, the load current transient is posive and the
voltage from the regulator might dip while the regulator circuit adapts to the new load
condions. Conversely, when the operang state of the GTM transceiver goes from power up to
power down, the load current transient is negave, and the voltage from the regulator might
spike while the regulator circuit adapts to the new load current condions. The magnitude and
duraon of the voltage transient from the power supply regulator depends upon the design of
the power supply regulator circuit. In some cases, the voltage might oscillate as the voltage
regulator circuit converges to the design voltage seng. In all of these cases, the important
consideraon is that the voltage at the input pin of the device must remain within the operang
limits as specied in the UltraScale+ device data sheets (see hp://www.xilinx.com/
documentaon). Use the Xilinx Power Esmator (XPE) tool to calculate the amount of power
required for the transceivers in your applicaon.
Power Supply Regulators
Normally, the GTM transceiver analog voltage supplies have local power supply regulators that
provide a nal stage of voltage regulaon. Preferably these regulators are placed as close as is
feasible to the GTM transceiver power supply pins. Minimizing the distance between the analog
voltage regulators and the GTM transceiver power supply pins reduces the opportunity for noise
coupling into the supply aer the regulator and for noise generated by current transients caused
by load dynamics.
Chapter 5: Board Design Guidelines
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 126
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English