Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 54: Interfacing an LVPECL Oscillator to the GTM Transceiver Reference Clock
Input
LVPECL Oscillator
240Ω
240Ω
0.01 µF
0.01 µF
GTM Transceiver
Reference Clock
Input Buffer
Internal to
UltraScale+ Device
X20935-053118
Notes relevant to the gure:
1. The resistor values are nominal. Refer to the oscillator data sheet for actual bias resistor
requirement.
2. Before compleon of device conguraon, the terminaon resistor is not calibrated and the
voltage level input to the clock input buer should be made sure to not exceed the absolute
maximum rang as described in the UltraScale+ device data sheets (see hp://
www.xilinx.com/documentaon).
AC Coupled Reference Clock
AC coupling of the oscillator reference clock output to the GTM transceiver Dual reference clock
inputs serves mulple purposes:
• Blocking a DC current between the oscillator and the GTM transceiver Dual dedicated clock
input pins (which reduces the power consumpon of both parts as well).
• Common mode voltage independence.
• The AC coupling capacitor forms a high-pass lter with the on-chip terminaon that
aenuates wander of the reference clock.
To minimize noise and power consumpon, external AC coupling capacitors between the
sourcing oscillator and the GTM transceiver Dual dedicated reference clock input pins are
required.
Chapter 5: Board Design Guidelines
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 124
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English