Xilinx Virtex UltraScale+ FPGAs User Manual

Table 74: GTM Transceiver PCB Design Checklist (cont'd)
Pins Recommendations
MGTMRXP[1:0]
MGTMRXN[1:0]
• Use AC coupling capacitors for connection to transmitter. The recommended value for AC
coupling capacitors is 100 nF.
• Receiver data traces should be provided enough clearance to eliminate crosstalk from
adjacent signals.
• If a receiver will never be used under any conditions, connect the associated pin pair to GND.
• If a receiver is not used and not connected to anything under some conditions, but might be
connected to something and used under other conditions, or if a receiver is not used but
connected for future use, then for the conditions when the receiver is unused, either do not
instance the GTM transceiver in the FPGA design, or if the GTM transceiver is instanced, set
RXPD[1:0] to 2’b11.
• See RX Analog Front End.
MGTMTXP[1:0]
MGTMTXN[1:0]
• Transmitter should be AC coupled to the receiver. The recommended value for the AC
coupling capacitors is 100 nF.
• Transmitter data traces should be provided enough clearance to eliminate crosstalk from
adjacent signals.
• If a transmitter is not used, leave the associated pin pair unconnected.
MGTAVTTRCAL
• Connect to MGTAVTT and to a 100Ω resistor that is also connected to MGTRREF. Use identical
trace geometry for the connection between the resistor and this pin, and for the connection
from the other pin of the resistor to MGTRREF. Also, the DC resistance of the PCB trace should
be limited to less than 0.5Ω.
• See Termination Resistor Calibration Circuit.
• If an entire PSG is not used by any Duals, tie MGTAVTTRCAL to ground.
MGTRREF
• Connect to a 100Ω resistor that is also connected to MGTAVTTRCAL. Use identical trace
geometry for the connection between the resistor to this pin, and for the connection from the
other pin of the resistor to MGTAVTTRCAL. Also, the DC resistance of the PCB trace should be
limited to less than 0.5Ω.
• See Termination Resistor Calibration Circuit.
• If an entire PSG is not used by any Duals, tie MGTRREF to ground.
Chapter 5: Board Design Guidelines
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 130
Send Feedback

Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English