Xilinx Virtex UltraScale+ FPGAs User Manual

Termination Resistor Calibration Circuit
One resistor calibraon circuit (RCAL) is shared between all GTM transceiver DUAL primives in
a GTM transceiver Dual column. The MGTAVTTRCAL and MGTRREF pins connect the bias
circuit power and the external calibraon resistor to the RCAL circuit. The RCAL circuit performs
the resistor calibraon only during conguraon of the UltraScale+ device. Prior to conguraon,
all analog supply voltages must be present and within the proper tolerance as specied in the
UltraScale+ device data sheets (see hp://www.xilinx.com/documentaon). If an enre power
supply group (PSG) is not used by any Duals, MGTAVTTRCAL and MGTRREF should be ed to
ground. See Analog Power Supply Pins for more details regarding RCAL biasing recommendaons
when there are unused Duals.
The RCAL circuit is associated with the GTM transceiver Dual that is the RCAL master. The RCAL
master performs the terminaon resistor calibraon during conguraon of the UltraScale+
device and then distributes the calibrated values to all of the GTM transceiver Duals in the
column. The Dual in which the RCAL circuit is located must be powered on. For Stacked Silicon
Interconnect (SSI) technology devices, each slice to be used (that contains mulple Duals) must
be powered on.
Connect the MGTAVTTRCAL pin to the MGTAVTT supply and to a pin on the 100Ω precision
external resistor. The other pin of the resistor is connected to the MGTRREF pin. The resistor
calibraon circuit provides a controlled current load to the resistor connected to the MGTRREF
pin. It then senses the voltage drop across the external calibraon resistor and uses that value to
adjust the internal resistor calibraon seng. The quality of the resistor calibraon is dependent
on the accuracy of the voltage measurement at the MGTAVTTRCAL and MGTRREF pins. To
eliminate errors due to the voltage drop across the traces that lead from the resistor and to the
UltraScale+ device pins, the trace from the MGTAVTTRCAL pin to the resistor should have the
same length and geometry as the trace that connects the other pin of the resistor to the
MGTRREF pin. Also, the maximum DC resistance of the PCB trace must be limited to less than
0.5Ω. (See the suggested layout in the following gure.)
Figure 47: PCB Layout for the RCAL Resistor
100Ω
Trace length from the resistor pins to the
FPGA pins MGTRREF and MGTAVTTRCAL
must be equal in length.
Connection
to AVTT
MGTAVTTRCAL
MGTRREF
X20930-053118
Chapter 5: Board Design Guidelines
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 119
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English