Xilinx Virtex UltraScale+ FPGAs User Manual

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
Addres
s
DRP
Bits
R/W Attribute Name Attribute Bits
Attribute
Encoding
DRP
Encoding
0x014 [15:0] R/W CH0_RX_CDR_CFG4A [15:0] 0–65535 0–65535
0x015 [15:0] R/W CH0_RX_CDR_CFG4B [15:0] 0–65535 0–65535
0x016 [15:0] R/W CH0_RX_CDR_CFG3A [15:0] 0–65535 0–65535
0x017 [15:0] R/W CH0_RX_CDR_CFG3B [15:0] 0–65535 0–65535
0x018 [15:0] R/W CH0_RX_CDR_CFG2A [15:0] 0–65535 0–65535
0x019 [15:0] R/W CH0_RX_CDR_CFG2B [15:0] 0–65535 0–65535
0x01a [15:0] R/W CH0_RX_CDR_CFG1A [15:0] 0–65535 0–65535
0x01b [15:0] R/W CH0_RX_CDR_CFG1B [15:0] 0–65535 0–65535
0x01c [15:0] R/W CH0_RX_CDR_CFG0A [15:0] 0–65535 0–65535
0x01d [15:0] R/W CH0_RX_CDR_CFG0B [15:0] 0–65535 0–65535
0x01e [15:0] R/W CH0_RX_CLKGN_CFG1 [15:0] 0–65535 0–65535
0x01f [15:0] R/W CH0_RX_ANA_CFG2 [15:0] 0–65535 0–65535
0x020 [15:0] R/W CH0_RX_APT_CTRL_CFG2 [15:0] 0–65535 0–65535
0x021 [15:0] R/W CH0_RX_APT_CTRL_CFG3 [15:0] 0–65535 0–65535
0x022 [15:0] R/W CH0_RX_APT_CFG0A [15:0] 0–65535 0–65535
0x023 [15:0] R/W CH0_RX_APT_CFG0B [15:0] 0–65535 0–65535
0x024 [15:0] R/W CH0_RX_APT_CFG1A [15:0] 0–65535 0–65535
0x025 [15:0] R/W CH0_RX_APT_CFG1B [15:0] 0–65535 0–65535
0x026 [15:0] R/W CH0_RX_APT_CFG2A [15:0] 0–65535 0–65535
0x027 [15:0] R/W CH0_RX_APT_CFG2B [15:0] 0–65535 0–65535
0x028 [15:0] R/W CH0_RX_APT_CFG3A [15:0] 0–65535 0–65535
0x029 [15:0] R/W CH0_RX_APT_CFG3B [15:0] 0–65535 0–65535
0x02a [15:0] R/W CH0_RX_APT_CFG4A [15:0] 0–65535 0–65535
0x02b [15:0] R/W CH0_RX_APT_CFG4B [15:0] 0–65535 0–65535
0x02c [15:0] R/W CH0_RX_APT_CFG5A [15:0] 0–65535 0–65535
0x02d [15:0] R/W CH0_RX_APT_CFG5B [15:0] 0–65535 0–65535
0x02e [15:0] R/W CH0_RX_APT_CFG6A [15:0] 0–65535 0–65535
0x02f [15:0] R/W CH0_RX_APT_CFG6B [15:0] 0–65535 0–65535
0x030 [15:0] R/W CH0_RX_APT_CFG7A [15:0] 0–65535 0–65535
0x031 [15:0] R/W CH0_RX_APT_CFG7B [15:0] 0–65535 0–65535
0x032 [15:0] R/W CH0_RX_APT_CFG8A [15:0] 0–65535 0–65535
0x033 [15:0] R/W CH0_RX_APT_CFG8B [15:0] 0–65535 0–65535
0x034 [15:0] R/W CH0_RX_APT_CFG9A [15:0] 0–65535 0–65535
0x035 [15:0] R/W CH0_RX_APT_CFG9B [15:0] 0–65535 0–65535
0x036 [15:0] R/W CH0_RX_APT_CFG10A [15:0] 0–65535 0–65535
0x037 [15:0] R/W CH0_RX_APT_CFG10B [15:0] 0–65535 0–65535
0x038 [15:0] R/W CH0_RX_APT_CFG11A [15:0] 0–65535 0–65535
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 134
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English