2-22 MAC™ 5000 resting ECG analysis system Revision B
2024917-010
Equipment Overview: Theory of Operation
System Interrupt Timer
A 1KHz timer generates system interrupts (which may be routed to FIQ
or IRQ) once every millisecond. This interrupt provides the foundation
for all operating system timers.
Acquisition Module Interface
Overview
The MAC 5000 acquisition module communication protocol is different
from previous generations in several key respects:
1. Acquisition module timing is synchronized to the system.
There is no longer a need to play synchronizing games to get the
system (especially the display and printer) operating at the same
sampling rate as the acquisition module.
2. Data is framed and has checksum.
Previous acquisition modules offered rudimentary error detection.
This has finally been done nearly right. Each ECG data packet
contains a checksum.
3. Commands do not interrupt the data stream.
Previous generation acquisition modules required a cessation of
sampling to transmit commands to the module. This cessation of
sampling had the undesirable effect of breaking the acquisition
stream for operations as simple as changing the line filter frequency
or enabling or disabling the pace pulse detector. With the MAC 5000
this restriction is removed.
4. Buttons are supported.
Button state is communicated to the system in each ECG data
packet. This allows limited operator interaction with the machine via
the acquisition module.
Details
A constant reference clock frequency of 1MHz must be provided to the
acquisition module for generation of its internal sampling clocks. To
eliminate the need for data lines, command information is encoded on
this reference clock by altering its duty cycle. The FPGA provides a
serializer for the command bytes and clock generator/modulator to
transmit both the clock and command bits from the serializer. The
reference clock duty cycle is nominally 50%. By altering the duty cycle,
the DC content of the clock is changed. The acquisition module detects
this change in DC level. The timing of these shifts in DC offset encode
command data bits. A zero is encoded as a single shift in duty cycle from
50% to 25% lasting 31.25μs, followed by a refractory period of 468.8μs.
A one is encoded as a pair of 31.25μs periods of 25% duty cycle separated
by 93.75μs, followed by a 343.8μs refractory period. In either case the
transmission of a single bit takes 500μs. A higher level protocol organizes
commands as groups of 8 bits.
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