Quectel LTE-A Series User Manual

LTE-A Module Series
EG060V-EA Hardware Design
EG060V-EA_Hardware_Design 51 / 82
In order to enhance the module’s reliability and usability in applications, please follow the criteria below in
PCIe interface circuit design:
⚫ Keep PCIe data and control signals away from sensitive circuits and signals, such as RF, audio, and
19.2 MHz clock signals.
⚫ A capacitance should be added in series on Tx/Rx traces to remove any DC bias.
⚫ Keep the maximum trace length less than 300 mm.
⚫ The length difference of the Tx or Rx differential pair of PCle traces should be less than 0.7 mm.
⚫ The differential impedance of PCIe data traces should be 100 Ω ±10 %.
⚫ PCIe data traces must not be routed under components or crossing other traces.
“*” means under development.
3.18. WLAN Control Interface*
EG060V-EA provides a low power PCIe interface* and a control interface for WLAN design. The following
table shows the pin definition of WLAN control interface.
Table 22: Pin Definition of WLAN Control Interface
If unused, keep it open.
PCIE_RST_N
189
IO
PCIe reset
In master mode, it is an output
signal.
In slave mode, it is an input signal.
If unused, keep it open.
PCIE_WAKE_N
190
IO
PCIe wake up
In master mode, it is an input signal.
In slave mode, it is an output signal.
If unused, keep it open.
Pin Name
Pin No.
I/O
Description
Comment
WLAN_PWR_EN
5
DO
WLAN power supply enable control
1.8 V power domain
WLAN_WAKE
160
DI
Wake up the host by an external
Wi-Fi module
1.8 V power domain
WLAN_EN
149
DO
WLAN function enable control
1.8 V power domain
COEX_RXD
146
DI
LTE&WLAN coexistence receive
1.8 V power domain
NOTE

Quectel LTE-A Series Specifications

General

Brand	Quectel
Model	LTE-A Series
Category	Control Unit
Language	English