14. Serial I/O
puorG92/C61M
page 207
854fo7002,03.raM21.1.veR
2110-1010B90JER
Table 14.16 Registers to Be Used and Settings in Special Mode 2
Register Bit Function
U2TB
(1)
0 to 7 Set transmission data
U2RB
(1)
0 to 7 Reception data can be read
OER Overrun error flag
U2BRG 0 to 7 Set bit rate
U2MR
(1)
SMD2 to SMD0 Set to 0012
CKDIR Set this bit to 0 for master mode or 1 for slave mode
IOPOL Set to 0
U2C0 CLK1, CLK0 Select the count source for the U2BRG register
CRS Invalid because CRD is set to 1
TXEPT Transmit register empty flag
CRD Set to 1
NCH Select TxD2 pin output format
CKPOL
Clock phases can be set in combination with the CKPH bit in the U2SMR3 register
UFORM Select the LSB first or MSB first
U2C1 TE Set this bit to 1 to enable transmission
TI Transmit buffer empty flag
RE Set this bit to 1 to enable reception
RI Reception complete flag
U2IRS Select UART2 transmit interrupt cause
U2RRM, Set to 0
U2LCH, U2ERE
U2SMR 0 to 7 Set to 0
U2SMR2 0 to 7 Set to 0
U2SMR3 CKPH Clock phases can be set in combination with the CKPOL bit in the U2C0 register
NODC Set to 0
0, 2, 4 to 7 Set to 0
U2SMR4 0 to 7 Set to 0
NOTE:
1.Not all bits in the registers are described above. Set those bits to 0 when writing to the registers in Special Mode 2.
Figure 14.26 Serial Bus Communication Control Example (UART2)
P13
P12
P70(TxD2)
P7
2(CLK2)
P7
1(RxD2)
P93
P70(TxD2)
P7
2(CLK2)
P7
1(RxD2)
P93
P70(TxD2)
P7
2(CLK2)
P7
1(RxD2)
MCU
(Master)
MCU
(Slave)
MCU
(Slave)
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