puorG92/C61M
22. Usage Notes
page 445
854fo7002,03.raM21.1.veR
2110-1010B90JER
22.12 Programmable I/O Ports
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1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to 1
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(three-phase output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to
a high-impedance state.
2. The input threshold voltage of pins differs between programmable input/output ports and peripheral
functions.
Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the
input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither
“high” nor “low”), the input level may be determined differently depending on which side—the program-
mable input/output port or the peripheral function—is currently selected.
3.When the SM32 bit in the S3C register is set to 1, the P32 pin goes to high-impedance state. When the
SM42 bit in the S4C register is set to 1, the P96 pin goes to high-imepdance state.
4. When the INV03 bit in the INVC0 register is 1(three-phase motor control timer output enabled), an "L"
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input on the P85 /NMI/SD pin, has the following effect.
•When the TB2SC register IVPCR1 bit is set to 1 (three-phase output forcible cutoff by input on
_____ __ __ ___
SD pin enabled), the U/ U/ V/ V/ W/ W pins go to a high-impedance state.
•When the TB2SC register IVPCR1 bit is set to 0 (three-phase output forcible cutoff by input on
_____ __ __ ___
SD pin disabled), the U/ U/ V/ V/ W/ W pins go to a normal port.
Therefore, the P85 pin can not be used as programmable I/O port when the INV03 bit is set to 1.
_____ _______ _____
When the SD function isn't used, set to 0 (Input) in PD85 and pullup to H in the P85 /NMI/SD pin from
outside.
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