Renesas M16C/29 Series User Manual

14. Serial I/O
puorG92/C61M
page 211
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Figure 14.30 Bus Collision Detect Function-Related Bits
(2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)
(1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
Timer A0
(3) The SSS bit in the U2SMR register (Transmit start condition select)
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (Note 1) of RxD2
TxD2
CLK2
TxD2
RxD2
TxD2
RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
Input to TA0 IN
If ABSCS is set to 1, bus collision is determined when timer
A0 (one-shot timer mode) underflows
.
TxD2
RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 D8
SP
Transfer clock
BCNIC register
IR bit (Note)
U2C1 register
TE bit
If ACSE bit is set to 1
automatically clear when bus collision
occurs), the TE bit is cleared to 0
(transmission disabled) when
the IR bit in the BCNIC register is
set to 1 (unmatching detected).
If SSS bit is set to 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
(Note 2)
NOTES:
1: The falling edge of RxD2 when the IOPOL is set to 0; the rising edge of RxD2 when the IOPOL is set to 1.
2: The transmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where the IOPOL is set to 1 (reversed)
.

Renesas M16C/29 Series Specifications

General

Brand	Renesas
Model	M16C/29 Series
Category	Microcontrollers
Language	English