Tektronix FG 5010 User Manual

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Diagram 5. Thus , the RD signal allows the buffers to be
enabled
only
during
a
read operation .
This prevents the
bus
contention
that would
result if a
write operation
were
select
ed
while
the FI
signal is
low (
during
Kernel
testing
)
.
Note that
data
outputs D0
through D5
are
produced by
the
Address
Switch
circuits .
Data bits D6
and
D7 are
pro
duced
by
Sa / Cal /
Norm jumper
P1121
. In
the
normal
jumper
position
,
both D6
and D7
outputs
on
the bus
are low (
high
into
buffer U1232A
because of the
pull - up
resistors
)
. In the
Cal position , the CAL input to U1232A is low , which results
in a high output on the data bus for D6 . This causes the
FG
5010 to
assume the
calibration
mode
at
power
- on
. In the
Sa position , the SA input to U1232A
low
,
which results
in
a high D7 output . This causes the FG 5010 to assume the
signature
analysis
mode at
power - on .
( 2 ) FRONT - PANEL SECTION
The front - panel
circuits are
depicted on diagram 2
at the
rear of the instruction manual . Refer to this diagram while
reading this description . The circuits depicted consist of
three sections . The first is the keyboard , which consists of
the 43 control keys of the FG 5010. The keys are connected
in a matrix to allow the keys to be scanned and debounced
by the keyboard and display interfaces . The column and row
lines from the keys are connected to the interface bus for
use
by the
CPU
circuits .
DISPLAY SECTION
The
second
of
the
circuits is the
segmented
display ,
which
consists
of six
7 -
segment units (
one of
which
displays
the exponent , and another that displays the sign of the
exponent ) . All of the display units are driven by the same
source in a time - share method , which refreshes the
complete array
of display units
at a refresh rate
of 100 Hz .
This rate is well above the flicker rate that is discernible to
the eye , so the display appears to be continously
illuminated .
The third of the front - panel circuits is the LED indicator
section , which consists of 32 LED lamps that indicate the
status of the various functions . Twenty - nine of these lamps
are controlled by the same selection matrix as that
controlling the segmented display units . Thus , these lamps
also illuminate on a time - share basis at a 100 Hz refresh
rate . The three remaining lamps , which illuminate the
TRIG'D , ERROR , and NOT ENTERED indicators , are
directly
driven by the
CPU
circuits .
@
Theory of Operation - FG 5010
Power
Supply Connections
Power
is
supplied to the
Processor
Board
through
edge
connector P1010 , pins 1A , 1B ,
and 2A ; ground
is
connected
through pins 3A , 3B , 4A , 4B , 5A , and 5B . Parallel lines are
used for
the
power
connections to
reduce
voltage
drops
across the connectors . Capacitors C1900 and C1920 and
inductor L1910
are a pi LC filter
network to reduce
the noise
applied from the Processor Board to the rest of the FG 5010
over the +5
V bus . In
addition
to
C1920
,
distributed
capaci
tance
throughout the
Processor Board is
used to provide
the
return
path for the
high -
frequency
noise currents
gener
ated by the logic elements .
( 3 > FRONT - PANEL DRIVE
Display
Decodor
The decodor consists of four - to - ten - line decoders U1134
and U1230 , the latter of which is connected as a three to
six - line decodor . These units are driven by the four select
lines from the CPU ( lines SLO , SL1 , SL2 , and SL3 ) . The
lines are cycled in binary order from all zeroes through all
ones . ( SLO is the least significant bit , and SL3 is the most
significant bit . ) Since the cycle rate of the select lines is
100 Hz ( i.e. , the lines go from all zeroes to all ones in
10 ms ) , each of the outputs of U1134 is low for about
640 μs during each 10 ms period . Since SL3 does not go to
U1230 , only outputs through 7 are active . Each active
output of U1230 is low for about 640 µs twice during each
10
ms
period .
From the output of U1134 , lines through 8 drive the
base of Display Driver transistors Q1011 through Q1020 ,
respectively . These nine drivers control the current to the
front
- panel
indicators
and numerals
.
Line 9 of the decoder furnishes a trigger to one - shot
U1232B . The period of this one - shot is set by C1222 and
R1224 to be slightly longer than the 10 ms recurrence time
of the incoming trigger . Thus , if the front panel is being re
freshed at the proper rate , the output of U1232B is
continously low . If the Display Driver circuit on the CPU
board is not operating properly , the trigger from U1134 will
hot occur , and U1232B will not continue to cycle . The out
put of the one - shot will move high , and the current to the
4-61

Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English