Tektronix FG 5010 User Manual

Theory
of
Operation - FG
5010
LOOP 2 SECTION
INTRODUCTION
The Loop 2 section consists of the following major
circuits , which are depicted on Diagrams 12 through 19 :
Trigger circuits , Phase Lock circuits , Low - Frequency
Generator , and Frequency Control . Since they are part of
the
Loop 2
subassembly
, the
Trigger
circuits and
Phase
Lock circuits are included in the following Block Diagram
description . However , since neither are considered part of
the main signal path , they are discussed later in this section ,
under the heading Trigger , Phase Lock , and N Burst
circuits . Also , the Digital Control circuits are discussed as a
group
following
the Block
Diagram description
.
The Loop 2 circuits form the low - frequency digital
counterpart of Loop 1. The generation of any triangle wave
signal that is below 200 Hz is the function of the Loop 2
circuits . The squarewave signal from Loop 1 is applied to
the Loop 2 circuits , which divide the signal by 100,000 and
use it to build a digital staircase signal that consists of 1000
increments and 1000 decrements . The result is applied to
the Function selector for application to the Sine Shaper or
Output
Amplifier
circuits .
BLOCK DIAGRAM DESCRIPTION
Refer to the Loop 2 Block Diagram . The external trigger
is applied to the Trig / Gate Input Amplifier , which shapes the
signal and applies it to the Slope Selector and Phase
Detector Logic . The Slope selector chooses either the
positive or negative excursion of the trigger signal by
inverting it or not , and applies the signal to the Trigger
Status Sensor , and to the Loop 1 Logic . The Trigger Status
Sensor output informs the CPU of the existence and
frequency of the trigger signal .
The Phase
Detector
Logic
compares the
frequency of the
trigger signal to that of the Loop 1 square wave . The output
causes the Charge Pump to draw current from or force
current into the
Lock Filter ,
which is an
integrator
with
selectable capacitance . The output voltage is applied to the
Frequency Reference Selector in the Loop 1 circuits , and to
the over and underrange Detector , which informs the CPU
as to the
comparison of
trigger and
squarewave
signals
.
The Phase Detector Logic also feeds the Lock Detector ,
which informs
the CPU that the
two signals are
locked , or
not
.
The squarewave signal from Loop 1 is applied to the
+ 1 / + 10 circuit for application to the Loop Cycle Counter ,
4-22
which counts down from a number that is preset by the
CPU . The Count Gate Control uses the output of the Loop
Cycle
counter to
control the Gate ,
which
applies the 4 MHz
signal from
the
Clock Shaper
to the
Reference
Counter . By
counting the 4 MHz cycles that are permitted to pass
through the Gate , the CPU can determine the frequency
accuracy
of the
Loop 1
signal .
The
squarewave
signal
from the
HFSQ
Buffer is
also
applied to the Variable Symmetry Counter , which divides
the
incoming
signal by a
programmed
number for
each low
frequency
triangle slope .
That is , if the
symmetry
is 20-80 ,
then the divisor during up slope is 20 and during down slope
is
80. The
incoming frequency
is set so that
the
number
of
output
cycles is 1000
up slope and
1000 down
slope . The
output of this counter is fed to the Integral Cycle Counter .
This counter keeps track of how many increments have
occurred from the Variable Symmetry Counter , and stops
the
incoming
signal at
increments of 2000.
( This makes
sure
that a cycle is not stopped before completion . ) It also
implements the HOLD function , to stop a low - frequency
signal at
a point
determined
by the
CPU
.
The Max - Min Count Detector senses the output of the
LF Generator Counter , reversing the count each time the
counter reaches 1000 or 0. This stage also produces the LF
squarewave to
Loop 1. The
LF Generator
Counter is preset
to
the start point
by the CPU ,
then increments
with each
cycle from the Variable Symmetry Counter . The output of
the LF Generator Counter is fed to the LF Triangle DAC ,
which produces a dc voltage that is proportional to the
counter output .
The
resulting triangle - wave
signal passes
through the LF Triangle Buffer , then is applied to the Loop 1
circuits .
DIGITAL CONTROL CIRCUITS
CPU access to the Loop 2 circuits is through the Digital
Control circuits , which consist of two serial - parallel shift reg
isters . The first of the two registers consist of five eight - bit
latches , U1422 , U1520 , U1620 ( all on Diagram 17 ) , U1420 ,
and U1510 ( both on Diagram 18 ) . When a charge is to be
made
to one or
more bits in the
register , the forty
- bit word is
applied to the
input of U1520
, which is first
in line to
receive
data . The clock pulse is applied simultaneously , so forty
pulses
later , the
entire register
is loaded
. Then , the
STROBE 2L2 signal is asserted to transfer the serially - intro
duced data to the output lines . Figure 4-12 shows the Digital
Control circuit configuration , and lists the circuits controlled
by each latch . Note that U1620 and U1520 are also con
trolled by LOW FREQ SQWV and LOW FREQ SQWV , re
spectively . These
two
latches are
alternately
enabled by
these signals to control common output lines .
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Tektronix FG 5010 Specifications

General

Brand	Tektronix
Model	FG 5010
Category	Portable Generator
Language	English