Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 143
UG196 (v1.3) May 25, 2007
Oversampling
R
Oversampling
Overview
Each GTP transceiver includes built-in 5x oversampling to enable serial rates from
100 Mb/s to 500 Mb/s. At these low rates, the regular CDR must operate at 5x the desired
line rate to stay within its operating limits.
The digital oversampling circuit takes parallel data from the SIPO at 5x the desired line rate
and uses the position of bit value transitions to recover a clock. The transition points are
also used to pick an optimal sampling point to recover 2 bits of data from each set of 10 bits
presented.
Ports and Attributes
Table 7-15 defines the ports for built-in digital oversampling.
Figure 7-8: GTP RX Block Diagram
RX-PMA RX-PCS
Rx
EQ
Rx
OOB
SIPO
RX
Polarity
Over-
sampling
UG196_c7_08_092606
Rx
CDR
Shared
PMA
PLL
Divider
- Takes data from 10-bit datapath at 5x line rate
- Recovers clock at correct rate using digital algorithm
- Recovers data at the desired rate by extracting 2 bits for each 10
- Remaining datapath uses width selected by INTDATAWIDTH
- Set to operate at 5x desired line rate
- Datapath is automatically set to 10 bits wide
Table 7-15: RX DCDR Ports
Port Dir Clock Domain Description
RXENSAMPLEALIGN0
RXENSAMPLEALIGN1
In RXUSRCLK2
When High, the 5X oversampler in the
PCS continually adjusts its sample point.
When Low, it samples only at the point
that was active before the port went Low.
RXOVERSAMPLEERR0
RXOVERSAMPLEERR1
Out RXUSRCLK2
When High, indicates the FIFO in
oversampling circuit has either
overflowed or underflowed. PCS must be
reset to resume proper operation.

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English